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ds07-16901-1e fujitsu semiconductor data sheet copyright?2006 fujitsu li mited all rights reserved ?check sheet? is seen at the following support page url : http://jp.fujitsu.com/microelectr onics/products/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 32-bit proprietary microcontrollers cmos fr60 mb91470/480 series mb91482/f475/f478/f479/f487 mb91fv470 description the mb91470/480 series is fujitsu's general-purpose 32- bit risc microcontroller, which is designed for embedded control applications that r equire high-speed processing performance. this series uses the fr60 cpu, which is compatible with the fr* family of cpus. * : fr, the abbreviation of fujitsu risc contro ller, is a line of products of fujitsu limited. features ? fr60 cpu 32-bit risc, load/store architecture, five-stage pipeline operating frequency of 80 mhz (pll clock multiplied) 16-bit fixed-length instructions (basic instructions) instruction execution speed : one instruction per cycle memory-to-memory transfer, bit processing, barrel shift instructions, etc. : instructions suitable for embedded applications function entry and exit instructions, multi load/ store instructions of register contents : instructions compatible with c language. register interlock function to facilitate assembly-language coding built-in multiplier/instruction-level support ? signed 32-bit multiplication : 5 cycles ? signed 16-bit multiplication : 3 cycles interrupts (save pc and ps) : 6 cycles, 16 priority levels harvard architecture allowing program access and data access to be executed simultaneously instructions compatible with the fr family (continued)
mb91470/480 series 2 ? built-in peripheral functions combinations of built-in fl ash/rom and ram capacities i/o ports nmi (non maskable interrupt) external interrupts bit search module (for realos) function to search for the position of the first bit that has changed from 1 to 0 in a word starting from the msb 16-bit reload timers timing generator 8/16-bit ppg timers multi-function timer ? 16-bit free-run timer ? input capture (linked to free-run timer) ? output compare (linked to free-run timer) ? a/d start up compare (linked to free-run timer) ? wave form generator various wave forms are generated by using output co mpare output, 16-bit ppg timer and 16-bit dead timer. base timer only one timer function can be select ed from the 16-bit pwm timer, 16-bit ppg timer, 16/32-bit reload timer, and 16/32-bit pwc timer. 8/16-bit up/down counter multi-function serial interface ? full-duplex double buffer ? with 16-byte fifo ? asynchronous (start-stop synchronization) comm unication, clock synchronous communication, i 2 c* standard mode (max 100 kbps), i 2 c high-speed mode (selectable various modes at maximum of 400 kbps) ? selectable parity on/off ? each channel has built-in baud rate generator ? error detection function for parity, frame and overrun errors ? external clock can be used as transfer clock ? with i 2 c function 8/10-bit a/d converter (successive comparison type) ? resolution : 8-bit or 10-bit resolution selectable ? conversion time : 1.2 s (minimum conversion time for 33 mhz system clock) 1.2 s (minimum conversion time for 40 mhz system clock) (continued) mb91470 series mb91480 series 144 pins 100 pins flash mask flash mask 256 kbytes/16 kbytes mb91f475 ?? mb91482 384 kbytes/24 kbytes mb91f478 ??? 512 kbytes/32 kbytes mb91f479 ? mb91f487 ?
mb91470/480 series 3 (continued) 12-bit a/d converter (succe ssive approximation type) ? resolution : 12 bits ? conversion time : 2.0 s (minimum conversion time for 33 mhz system clock) 2.2 s (minimum conversion time for 40 mhz system clock) ? differential input mode is available. clock monitor ? peripheral clock (clkp) divided by 2/4/8/16/32/64/128/256 can be output. multiplication and addition calculator ? ram : instruction ram (i-ram) 256 16-bit factor ram (x-ram) 64 32-bit variable ram (y-ram) 64 32-bit ? high-speed multiplication and additi on (seven-stage pipeline processing) ? product addition (32-bit 32-bit + 72-bit) ? operation result is extracted rounded from 72 bits to 32 bits or 72-bit result data reading. dmac (dma controller) ? transfers can be started by software or by interrupts from the built-in peripherals. wild register ? instructions or data located at a target address can be replaced (in the built-in flash/rom area only) . ? external bus interface maximum operating frequency of 40 mhz 16-bit address full output (64 kbytes space) capability 8/16-bit data output use of unused data/address pins as general-purpose i/o ports totally independent 3-area chip select outputs that can be se t at minimum of 64 kbytes. support of interface for various memory (sram, rom/flash) basic bus cycle : 2 cycles automatic wait cycle generator that can be programmed for each area and can insert waits external wait cycle using rdy input ? other features watchdog timer low-power consumption modes ? sleep/stop function cmos technologies : 0.18 m power supply : single power supply (vcc = 4.0 v to 5.5 v) * : purchase of fujitsu i 2 c components conveys a lic ense under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips.
mb91470/480 series 4 product lineup characteristics mb91470/480 series common eva mb91470 series mb91480 series mb91fv470 mb91f475 mb91f478 mb91f479 mb91f487 mb91482 pin number 224 pins 144 pins 100 pins built-in flash/rom capacity 512 kbytes (flash) 256 kbytes (flash) 384 kbytes (flash) 512 kbytes (flash) 512 kbytes (flash) 256 kbytes (rom) built-in ram capacity 40 kbytes 16 kbytes 24 kbytes 32 kbytes 32 kbytes 16 kbytes external bus yes yes ? i/o ports 160 113 77 external interrupts nmi 16 channels nmi 10 channels nmi 10 channels reload timer 2 channels 2 channels 2 channels timing generator 2 units 1 unit 2 units ppg 8-bit 16 channels 16-bit 8 channels 8-bit 8 channels 16-bit 4 channels 8-bit 16 channels 16-bit 8 channels multi-function timer 2 units 1 unit 2 units free-run timer 6 channels 3 channels 6 channels ocu 12 channels 6 channels 12 channels icu 8 channels 4 channels 8 channels a/d activation compare 6 channels 3 channels 6 channels wave form generator 12 channels 6 channels 12 channels base timer 6 channels 4 channels 4 channels up/down counter 2 channels 1 channel ? multi-function serial interface 6 units 6 units 3 units 8/10-bit a/d converter 4 channels 2 units 16 channels 1 unit 12 channels 1 unit 4 channels 2 units 10 channels 1 unit 12-bit a/d converter 4 channels 2 units 4 channels 2 units ? clock monitor 1 unit ? 1 unit multiplication and addition calculator 1 unit 1 unit 1 unit dmac 5 channels 5 channels 5 channels wild register 16 channels 16 channels 16 channels debug function dsu4 ??
mb91470/480 series 5 package and corresponding products : supported note : for details of each package, refer to ? package dimensions?. mb91470 series mb91480 series mb91f475 mb91f478 mb91f479 mb91f487 mb91482 fpt-100p-m20 (lqfp-0.50 mm) ? fpt-144p-m12 (lqfp-0.40 mm) ?? bga-144p-m06 (fbga-0.80 mm) ?? package series name
mb91470/480 series 6 pin assignment ? lqfp-144 (mb91470 series) (continued) (top view) (fpt-144p-m12) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 vcc p51/cs1x p52/cs2x p53/asx p54/rdx p55/wr0x p56/wr1x p60/sysclk p61/rdy pj0/tin0 pj1/tout0 pj2/tin1 pj3/tout1 pj4/tin2 pj5/tout2 pj6/tin3 pj7/tout3 vcc vss p80/int0 p81/int1 p82/int2 p83/int3 p84/int4/ppg4 p85/int5/ppg5 p86/int6/ppg6 p87/int7/ppg7 p90/int8 p91/int9 nmix pl0/ain0 pl1/bin0 pl2/zin0 initx vcc vss 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 ph5/sot3 ph4/sin3 ph3/sck3 ph2/sot2 ph1/sin2 ph0/sck2 pg5/sot1 pg4/sin1 pg3/sck1 pg2/sot0 pg1/sin0 pg0/sck0 avss10 avrh2 avcc10 pd3/an2-11 pd2/an2-10 pd1/an2-9 pd0/an2-8 pc7/an2-7 pc6/an2-6 pc5/an2-5/sot5 pc4/an2-4/sin5 pc3/an2-3/sck5 pc2/an2-2/sot4 pc1/an2-1/sin4 pc0/an2-0/sck4 vcc vss pe7/an4-3 pe6/an4-2 pe5/an4-1 pe4/an4-0 avrh4 avcc12 avrh3 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 avss12 pe3/an3-3 pe2/an3-2 pe1/an3-1 pe0/an3-0 pa4/adtg4 pa3/adtg3 pa2/adtg2 pm3/ppg3 pm2/ppg2 pm1/ppg1 pm0/ppg0 vcc vss c pp5/dtti0 pp4/cki0 vss x1 x0 md0 md1 md2 pp3/ic3 pp2/ic2 pp1/ic1 pp0/ic0 vss vcc pq5/rto5 pq4/rto4 pq3/rto3 pq2/rto2 pq1/rto1 pq0/rto0 vcc p00/d16 p01/d17 p02/d18 p03/d19 p04/d20 p05/d21 p06/d22 p07/d23 p10/d24 p11/d25 p12/d26 p13/d27 p14/d28 p15/d29 p16/d30 p17/d31 vss vcc p20/a00 p21/a01 p22/a02 p23/a03 p24/a04 p25/a05 p26/a06 p27/a07 p30/a08 p31/a09 p32/a10 p33/a11 p34/a12 p35/a13 p36/a14 p37/a15 p50/cs0x vss (top view) (lqfp-144p-m12) 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vss p50/cs0x p37/a15 p36/a14 p35/a13 p34/a12 p33/a11 p32/a10 p31/a09 p30/a08 p27/a07 p26/a06 p25/a05 p24/a04 p23/a03 p22/a02 p21/a01 p20/a00 vcc vss p17/d31 p16/d30 p15/d29 p14/d28 p13/d27 p12/d26 p11/d25 p10/d24 p07/d23 p06/d22 p05/d21 p04/d20 p03/d19 p02/d18 p01/d17 p00/d16 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 vcc pq0/rto0 pq1/rto1 pq2/rto2 pq3/rto3 pq4/rto4 pq5/rto5 vcc vss pp0/ic0 pp1/ic1 pp2/ic2 pp3/ic3 md2 md1 md0 x0 x1 vss pp4/cki0 pp5/dtti0 c vss vcc pm0/ppg0 pm1/ppg1 pm2/ppg2 pm3/ppg3 pa2/adtg2 pa3/adtg3 pa4/adtg4 pe0/an3-0 pe1/an3-1 pe2/an3-2 pe3/an3-3 avss12
mb91470/480 series 7 ? fbga-144 (mb91470 series) (continued) (top view) (bga-144p-m06) index12345678910111213 a 1 48 47 46 45 44 43 42 41 40 39 38 37 b 2 49 88 87 86 85 84 83 82 81 80 79 36 c 3 50 89 120 119 118 117 116 115 114 113 78 35 d 4 51 90 121 144 143 142 141 140 139 112 77 34 e 5 52 91 122 138 111 76 33 f 6 53 92 123 137 110 75 32 g 7 54 93 124 136 109 74 31 h 8 55 94 125 135 108 73 30 j 9 56 95 126 134 107 72 29 k 10 57 96 127 128 129 130 131 132 133 106 71 28 l 11 58 97 98 99 100 101 102 103 104 105 70 27 m12596061626364656667686926 n13141516171819202122232425 12345678910111213
mb91470/480 series 8 (continued) ? lqfp-100 (mb91480 series) (top view) (fpt-100p-m20) 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 25 vcc p 8 6/int6/ppg6 p 8 7/int7/ppg7 p90/int 8 /ppg 8 p91/int9/ppg9 nmix pm0/ppg0 pm1/ppg1 pm2/ppg2 pm 3 /ppg 3 pf0/clkpout pp0/ic0 pp1/ic1 pp2/ic2 pp 3 /ic 3 pp4/cki0 pp5/dtti0 v ss vcc pq0/rto0 pq1/rto1 pq2/rto2 pq 3 /rto 3 pq4/rto4 pq5/rto5 75 74 7 3 72 71 70 69 6 8 67 66 65 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 v ss pa1/adtg1 pa0/adtg0 pb7/an1- 3 pb6/an1-2 pb5/an1-1 pb4/an1-0 pb 3 /an0- 3 pb2/an0-2 pb1/an0-1 pb0/an0-0 av ss 10 avrh2 avcc10 pd1/an2-9 pd0/an2- 8 pc7/an2-7 pc6/an2-6 pc5/an2-5 pc4/an2-4 pc 3 /an2- 3 pc2/an2-2 pc1/an2-1 pc0/an2-0 v cc 100 99 9 8 97 96 95 94 9 3 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 8 0 79 7 8 77 76 v ss p 8 5/int5/ppg5 p 8 4int4/ppg4 p 83 /int 3 p 8 2/int2 p 8 1/int1 p 8 0/int0 pj7/tout 3 pj6/tin 3 pj5/tout2 pj4/tin2 pj 3 /tout1 pj2/tin1 pj1/tout0 pj0/tin0 ph2/ s ot2 ph1/ s in2 ph0/ s ck2 pg5/ s ot1 pg4/ s in1 pg 3 / s ck1 pg2/ s ot0 pg1/ s in0 pg0/ s ck0 vcc 26 27 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 49 50 p s 0/rto6 p s 1/rto7 p s 2/rto 8 p s3 /rto9 p s 4/rto10 p s 5/rto11 v cc v cc v ss pr0/ic4 pr1/ic5 pr2/ic6 pr 3 /ic7 pr4/cki1 pr5/dtti1 md2 md1 md0 x0 x1 v ss initx pa2/adtg2 v ss c
mb91470/480 series 9 pin descriptions (continued) pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 50 m6 42 md2 h, k mode pin 2 this pin sets the basic operating mode. connect this pin to either vcc or vss. use circuit type k on the flash memory model. 51 n6 43 md1 h, k mode pin 1 this pin sets the basic operating mode. connect this pin to either vcc or vss. use circuit type k on the flash memory model. 52 k5 44 md0 h, k mode pin 0 this pin sets the basic operating mode. connect this pin to either vcc or vss. use circuit type k on the flash memory model. 53 l6 45 x0 a clock (oscillation) input 54 k6 46 x1 a clock (oscillation) output 34 l1 48 initx i external reset input 30 j4 6 nmix h nmi (non maskable interrupt) input 109 a12 ? d16 c bit 16 of external data bus i/o pin p00 general-purpose i/o port 110 b12 ? d17 c bit 17 of external data bus i/o pin p01 general-purpose i/o port 111 a11 ? d18 c bit 18 of external data bus i/o pin p02 general-purpose i/o port 112 b11 ? d19 c bit 19 of external data bus i/o pin p03 general-purpose i/o port 113 c12 ? d20 c bit 20 of external data bus i/o pin p04 general-purpose i/o port 114 b10 ? d21 c bit 21 of external data bus i/o pin p05 general-purpose i/o port 115 a10 ? d22 c bit 22 of external data bus i/o pin p06 general-purpose i/o port 116 c11 ? d23 c bit 23 of external data bus i/o pin p07 general-purpose i/o port 117 c10 ? d24 c bit 24 of external data bus i/o pin p10 general-purpose i/o port
mb91470/480 series 10 (continued) pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 118 b9 ? d25 c bit 25 of external data bus i/o pin p11 general-purpose i/o port 119 a9 ? d26 c bit 26 of external data bus i/o pin p12 general-purpose i/o port 120 d10 ? d27 c bit 27 of external data bus i/o pin p13 general-purpose i/o port 121 c9 ? d28 c bit 28 of external data bus i/o pin p14 general-purpose i/o port 122 b8 ? d29 c bit 29 of external data bus i/o pin p15 general-purpose i/o port 123 a8 ? d30 c bit 30 of external data bus i/o pin p16 general-purpose i/o port 124 d9 ? d31 c bit 31 of external data bus i/o pin p17 general-purpose i/o port 127 a7 ? a00 c bit 0 of external address bus output pin p20 general-purpose i/o port 128 b7 ? a01 c bit 1 of external address bus output pin p21 general-purpose i/o port 129 c7 ? a02 c bit 2 of external address bus output pin p22 general-purpose i/o port 130 d7 ? a03 c bit 3 of external address bus output pin p23 general-purpose i/o port 131 a6 ? a04 c bit 4 of external address bus output pin p24 general-purpose i/o port 132 b6 ? a05 c bit 5 of external address bus output pin p25 general-purpose i/o port 133 c6 ? a06 c bit 6 of external address bus output pin p26 general-purpose i/o port 134 d6 ? a07 c bit 7 of external address bus output pin p27 general-purpose i/o port 135 a5 ? a08 c bit 8 of external address bus output pin p30 general-purpose i/o port
mb91470/480 series 11 (continued) pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 136 b5 ? a09 c bit 9 of external address bus output pin p31 general-purpose i/o port 137 c5 ? a10 c bit 10 of external address bus output pin p32 general-purpose i/o port 138 d5 ? a11 c bit 11 of external address bus output pin p33 general-purpose i/o port 139 a4 ? a12 c bit 12 of external address bus output pin p34 general-purpose i/o port 140 b4 ? a13 c bit 13 of external address bus output pin p35 general-purpose i/o port 141 c4 ? a14 c bit 14 of external address bus output pin p36 general-purpose i/o port 142 a3 ? a15 c bit 15 of external address bus output pin p37 general-purpose i/o port 143 a2 ? cs0x c external chip select 0 output p50 general-purpose i/o port 2b2 ? cs1x c external chip select 1 output p51 general-purpose i/o port 3c1 ? cs2x c external chip select 2 output p52 general-purpose i/o port 4c2 ? asx c external address strobe output p53 general-purpose i/o port 5b3 ? rdx c external read strobe output p54 general-purpose i/o port 6d2 ? wr0x c external write strobe output corresponding to bit 31 to bit 24 of external data bus i/o p55 general-purpose i/o port 7d1 ? wr1x c external write strobe output corresponding to bit 23 to bit 16 of external data bus i/o p56 general-purpose i/o port 8c3 ? sysclk c external clock output p60 general-purpose i/o port
mb91470/480 series 12 (continued) pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 9d3 ? rdy c external ready input p61 general-purpose i/o port 20 g2 94 int0 d external interrupt 0 input p80 general-purpose i/o port 21 g3 95 int1 d external interrupt 1 input p81 general-purpose i/o port 22 g4 96 int2 d external interrupt 2 input p82 general-purpose i/o port 23 h1 97 int3 d external interrupt 3 input p83 general-purpose i/o port 24 h2 98 int4 d external interrupt 4 input ppg4 output of ppg timer 4 p84 general-purpose i/o port 25 h3 99 int5 d external interrupt 5 input ppg5 output of ppg timer 5 p85 general-purpose i/o port 26 h4 2 int6 d external interrupt 6 input ppg6 output of ppg timer 6 p86 general-purpose i/o port 27 j1 3 int7 d external interrupt 7 input ppg7 output of ppg timer 7 p87 general-purpose i/o port 28 j2 4 int8 d external interrupt 8 input ppg8 output of ppg timer 8 p90 general-purpose i/o port 29 j3 5 int9 d external interrupt 9 input ppg9 output of ppg timer 9 p91 general-purpose i/o port ?? ? int10 d external interrupt 10 input ppg10 output of ppg timer 10 p92 general-purpose i/o port
mb91470/480 series 13 (continued) pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 ?? ? int11 d external interrupt 11 input ppg11 output of ppg timer 11 p93 general-purpose i/o port ?? ? int12 d external interrupt 12 input ppg12 output of ppg timer 12 p94 general-purpose i/o port ?? ? int13 d external interrupt 13 input ppg13 output of ppg timer 13 p95 general-purpose i/o port ?? ? int14 d external interrupt 14 input ppg14 output of ppg timer 14 p96 general-purpose i/o port ?? ? int15 d external interrupt 15 input ppg15 output of ppg timer 15 p97 general-purpose i/o port ?? 73 adtg0 d external trigger input of 8/10-bit a/d converter 0 pa0 general-purpose i/o port ?? 74 adtg1 d external trigger input of 8/10-bit a/d converter 1 pa1 general-purpose i/o port 65 l9 49 adtg2 d external trigger input of 8/10-bit a/d converter 2 pa2 general-purpose i/o port 66 k9 ? adtg3 d external trigger input of 12-bit a/d converter 3 pa3 general-purpose i/o port 67 n10 ? adtg4 d external trigger input of 12-bit a/d converter 4 pa4 general-purpose i/o port ?? 65 an0-0 g analog 0 input of 8/10-bit a/d converter 0 pb0 general-purpose i/o port ?? 66 an0-1 g analog 1 input of 8/10-bit a/d converter 0 pb1 general-purpose i/o port ?? 67 an0-2 g analog 2 input of 8/10-bit a/d converter 0 pb2 general-purpose i/o port
mb91470/480 series 14 (continued) pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 ?? 68 an0-3 g analog 3 input of 8/10-bit a/d converter 0 pb3 general-purpose i/o port ?? 69 an1-0 g analog 0 input of 8/10-bit a/d converter 1 pb4 general-purpose i/o port ?? 70 an1-1 g analog 1 input of 8/10-bit a/d converter 1 pb5 general-purpose i/o port ?? 71 an1-2 g analog 2 input of 8/10-bit a/d converter 1 pb6 general-purpose i/o port ?? 72 an1-3 g analog 3 input of 8/10-bit a/d converter 1 pb7 general-purpose i/o port 82 j12 52 an2-0 g analog 0 input of 8/10-bit a/d converter 2 sck4 clock i/o of multi-function serial interface 4 (not used in i 2 c mode) pc0 general-purpose i/o port 83 j13 53 an2-1 g analog 1 input of 8/10-bit a/d converter 2 sin4 data input of multi-function se rial interface 4 (not used in i 2 c mode) pc1 general-purpose i/o port 84 k10 54 an2-2 g analog 2 input of 8/10-bit a/d converter 2 sot4 data output of multi- function serial interface 4 pc2 general-purpose i/o port 85 j11 55 an2-3 g analog 3 input of 8/10-bit a/d converter 2 sck5 clock i/o of multi-function serial interface 5 pc3 general-purpose i/o port 86 h12 56 an2-4 g analog 4 input of 8/10-bit a/d converter 2 sin5 data input of multi-function se rial interface 5 (not used in i 2 c mode) pc4 general-purpose i/o port 87 h13 57 an2-5 g analog 5 input of 8/10-bit a/d converter 2 sot5 data output of multi- function serial interface 5 pc5 general-purpose i/o port 88 j10 58 an2-6 g analog 6 input of 8/10-bit a/d converter 2 pc6 general-purpose i/o port
mb91470/480 series 15 (continued) pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 89 h11 59 an2-7 g analog 7 input of 8/10-bit a/d converter 2 pc7 general-purpose i/o port 90 h10 60 an2-8 g analog 8 input of 8/10-bit a/d converter 2 pd0 general-purpose i/o port 91 g13 61 an2-9 g analog 9 input of 8/10-bit a/d converter 2 pd1 general-purpose i/o port 92 g12 ? an2-10 g analog 10 input of 8/10-bit a/d converter 2 pd2 general-purpose i/o port 93 g11 ? an2-11 g analog 11 input of 8/10-bit a/d converter 2 pd3 general-purpose i/o port 68 m10 ? an3-0/ an3-0p g 12-bit a/d converter 3 analog 0 input (in single input mode) 12-bit a/d converter 3 analog 0 ( + ) side input (in differential input mode) pe0 general-purpose i/o port 69 l10 ? an3-1/ an3-0n g 12-bit a/d converter 3 analog 1 input (in single input mode) 12-bit a/d converter 3 analog 0 ( ? ) side input (in differential input mode) pe1 general-purpose i/o port 70 n11 ? an3-2/ an3-1p g 12-bit a/d converter 3 analog 2 input (in single input mode) 12-bit a/d converter 3 analog 1 ( + ) side input (in differential input mode) pe2 general-purpose i/o port 71 n12 ? an3-3/ an3-1n g 12-bit a/d converter 3 analog 3 input (in single input mode) 12-bit a/d converter 3 analog 1 ( ? ) side input (in differential input mode) pe3 general-purpose i/o port 76 l12 ? an4-0/ an4-0p g 12-bit a/d converter 4 analog 0 input (in single input mode) 12-bit a/d converter 4 analog 0 ( + ) side input (in differential input mode) pe4 general-purpose i/o port 77 m11 ? an4-1/ an4-0n g 12-bit a/d converter 4 analog 1 input (in single input mode) 12-bit a/d converter 4 analog 0 ( ? ) side input (in differential input mode) pe5 general-purpose i/o port
mb91470/480 series 16 (continued) pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 78 k12 ? an4-2/ an4-1p g 12-bit a/d converter 4 analog 2 input (in single input mode) 12-bit a/d converter 4 analog 1 ( + ) side input (in differential input mode) pe6 general-purpose i/o port 79 k13 ? an4-3/ an4-1n g 12-bit a/d converter 4 analog 3 input (in single input mode) 12-bit a/d converter 4 analog 1 ( ? ) side input (in differential input mode) pe7 general-purpose i/o port ?? 11 clk- pout d clock monitor output pf0 general-purpose i/o port ?? ? pf1 d general-purpose i/o port ?? ? pf2 d general-purpose i/o port ?? ? pf3 d general-purpose i/o port ?? ? pf4 d general-purpose i/o port ?? ? pf5 d general-purpose i/o port ?? ? pf6 d general-purpose i/o port ?? ? pf7 d general-purpose i/o port 97 f11 77 sck0 d clock i/o of multi-function serial interface 0 pg0 general-purpose i/o port 98 f10 78 sin0 d data input of multi-function seri al interface 0 (not used in i 2 c mode) pg1 general-purpose i/o port 99 e13 79 sot0 d data output of multi-fu nction serial interface 0 pg2 general-purpose i/o port 100 e12 80 sck1 d clock i/o of multi-function serial interface 1 pg3 general-purpose i/o port 101 e11 81 sin1 d data input of multi-function seri al interface 1 (not used in i 2 c mode) pg4 general-purpose i/o port 102 e10 82 sot1 d data output of multi-fu nction serial interface 1 pg5 general-purpose i/o port 103 d13 83 sck2 d clock i/o of multi-function serial interface 2 ph0 general-purpose i/o port
mb91470/480 series 17 (continued) pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 104 d12 84 sin2 d data input of multi-function se rial interface 2 (not used in i 2 c mode) ph1 general-purpose i/o port 105 d11 85 sot2 d data output of multi-fu nction serial interface 2 ph2 general-purpose i/o port 106 c13 ? sck3 d clock i/o of multi-function serial interface 3 ph3 general-purpose i/o port 107 b13 ? sin3 d data input of multi-function se rial interface 3 (not used in i 2 c mode) ph4 general-purpose i/o port 108 a13 ? sot3 d data output of multi-fu nction serial interface 3 ph5 general-purpose i/o port 10 e2 86 tin0 d base timer 0 input pj0 general-purpose i/o port 11 e1 87 tout0 d base timer 0 output pj1 general-purpose i/o port 12 d4 88 tin1 d base timer 1 input pj2 general-purpose i/o port 13 e3 89 tout1 d base timer 1 output pj3 general-purpose i/o port 14 f2 90 tin2 d base timer 2 input pj4 general-purpose i/o port 15 f1 91 tout2 d base timer 2 output pj5 general-purpose i/o port 16 e4 92 tin3 d base timer 3 input pj6 general-purpose i/o port 17 f3 93 tout3 d base timer 3 output pj7 general-purpose i/o port 31 k1 ? ain0 d 8/16-bit up count input pin for up/down counter 0 pl0 general-purpose i/o port 32 k2 ? bin0 d 8/16-bit down count input pin for up/down counter 0 pl1 general-purpose i/o port
mb91470/480 series 18 (continued) pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 33 k3 ? zin0 d 8/16-bit reset input pin for up/down counter 0 pl2 general-purpose i/o port 61 l8 7 ppg0 d output of ppg timer 0 pm0 general-purpose i/o port 62 k8 8 ppg1 d output of ppg timer 1 pm1 general-purpose i/o port 63 n9 9 ppg2 d output of ppg timer 2 pm2 general-purpose i/o port 64 m9 10 ppg3 d output of ppg timer 3 pm3 general-purpose i/o port 46 m5 12 ic0 d trigger input of input capture 0 pp0 general-purpose i/o port 47 n5 13 ic1 d trigger input of input capture 1 pp1 general-purpose i/o port 48 k4 14 ic2 d trigger input of input capture 2 pp2 general-purpose i/o port 49 l5 15 ic3 d trigger input of input capture 3 pp3 general-purpose i/o port 56 m7 16 cki0 d external clock input pin of free-run timer ch.0 to ch.2 pp4 general-purpose i/o port 57 l7 17 dtti0 d input signal controlling wave form generator outputs rto0 to rto5 of multi-function timer 0 pp5 general-purpose i/o port 38 m2 20 rto0 j wave form generator output of multi-function timer 0 pq0 general-purpose i/o port 39 n3 21 rto1 j wave form generator output of multi-function timer 0 pq1 general-purpose i/o port 40 m3 22 rto2 j wave form generator output of multi-function timer 0 pq2 general-purpose i/o port 41 l2 23 rto3 j wave form generator output of multi-function timer 0 pq3 general-purpose i/o port
mb91470/480 series 19 (continued) * : refer to ? i/o circuit type? for i/o circuit type. pin no. pin name i/o circuit type* function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 42 m4 24 rto4 j wave form generator output of multi-function timer 0 pq4 general-purpose i/o port 43 n4 25 rto5 j wave form generator output of multi-function timer 0 pq5 general-purpose i/o port ?? 36 ic4 d trigger input of input capture 4 pr0 general-purpose i/o port ?? 37 ic5 d trigger input of input capture 5 pr1 general-purpose i/o port ?? 38 ic6 d trigger input of input capture 6 pr2 general-purpose i/o port ?? 39 ic7 d trigger input of input capture 7 pr3 general-purpose i/o port ?? 40 cki1 d external clock input pin of free-run timer ch.3 to ch.5 pr4 general-purpose i/o port ?? 41 dtti1 d input signal controlling wave form generator outputs rto6 to rto11 of multi-function timer 1 pr5 general-purpose i/o port ?? 26 rto6 j wave form generator output of multi-function timer 1 ps0 general-purpose i/o port ?? 27 rto7 j wave form generator output of multi-function timer 1 ps1 general-purpose i/o port ?? 28 rto8 j wave form generator output of multi-function timer 1 ps2 general-purpose i/o port ?? 29 rto9 j wave form generator output of multi-function timer 1 ps3 general-purpose i/o port ?? 30 rto10 j wave form generator output of multi-function timer 1 ps4 general-purpose i/o port ?? 31 rto11 j wave form generator output of multi-function timer 1 ps5 general-purpose i/o port
mb91470/480 series 20 power supply pins and gnd pins pin number pin name function mb91470 series mb91480 series lqfp- 144 fbga- 144 lqfp- 100 1 18 35 37 44 60 81 126 b1 f4 m1 n2 l3 m8 k11 d8 1 19 32 33 51 76 vcc power supply pins connect all pins to the same potential. 19 36 45 55 59 80 125 144 a1 g1 n1 l4 n7 n8 l11 c8 18 34 47 50 75 100 vss gnd pins connect all pins to the same potential. 58 k7 35 c capacitor coupling pin for internal regulator 94 g10 62 avcc10 analog power supply pi n for 8/10-bit a/d converter 0/1/2 96 f12 64 avss10 analog gnd pin for 8/10-bit a/d converter 74 m12 ? avcc12 analog power supply pin for 12-bit a/d converter 3/4 72 n13 ? avss12 analog gnd pin for 12 -bit a/d converter 3/4 ?? ? avrh0 analog reference power supply pin for 8/10-bit a/d converter 0 ?? ? avrh1 analog reference power supply pin for 8/10-bit a/d converter 1 95 f13 63 avrh2 analog reference power supp ly pin for 8/10-bit a/d converter 2 73 m13 ? avrh3 analog reference power supply pin for 12-bit a/d converter 3 75 l13 ? avrh4 analog reference power supply pin for 12-bit a/d converter 4
mb91470/480 series 21 i/o circuit type (continued) type circuit remarks a oscillation feedback resistance for high speed (main clock oscillation) approx. 1 m ? c cmos level output cmos level input with standby control with pull-up control d cmos level output cmos level hysteresis input with standby control with pull-up control x1 x0 clock input standby control r p-ch p-ch n-ch digital input pull-up control digital output digital output standby control r p-ch p-ch n-ch digital input pull-up control digital output digital output standby control
mb91470/480 series 22 (continued) type circuit remarks g analog/cmos level hysteresis i/o pin cmos level output cmos level hysteresis input (with standby control) analog input (operates as an analog input when the corresponding aicr register bit is ?1?.) with pull-up control h cmos level hysteresis input without standby control i cmos level hysteresis input without standby control with pull-up resistance r p-ch n-ch p-ch analog input digital input digital output digital output standby control pull-up control r n-ch p-ch digital input r p-ch p-ch n-ch digital input
mb91470/480 series 23 (continued) type circuit remarks j cmos level output cmos level hysteresis input with standby control with pull-up control k flash memory product only cmos level input high voltage control for testing flash memory r p-ch n-ch p-ch digital output digital output digital input standby control pull-up control r n-ch n-ch n-ch n-ch n-ch mode input control signal
mb91470/480 series 24 handling devices ? preventing latch-up latch-up phenomenon may occur with cmos ic, when a voltage higher than v cc or lower than v ss is applied to either the input or output terminals, or when a voltage is applied between v cc and v ss that exceeds the rated voltage. when latch-up occurs, a significant power-supply current surge results, which may damage some elements due to the excess heat, so great care must be taken to ensure that the maximum rating is never exceeded during use. ? treatment of unused input pins do not leave an unused input pin open, since it may cause a malfunction. handle by, for example, using a pull-up or pull-down resistor. ? power pins in products with multiple v cc and v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to the same potential power supply and a ground line externally to lower the electro- magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground leve l, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a ce ramic capacitor of approximately 0.1 f as a bypass capacitor between v cc and v ss near this device. ? crystal oscillator circuit noise near the x0 and x1 pins may cause the device to ma lfunction. design the printed circuit board so that x0, x1, the crystal oscillator (or ceramic oscillator), and the by pass capacitor to ground ar e located as close to the device as possible. it is strongly recommended to design the pc board artw ork with the x0 and x1pins surrounded by ground plane because stable operation can be expected with such a la yout. please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. ? about mode pins (md0 to md2) these pins should be connected directly to v cc pin or v ss pin. to prevent the device erroneously switching to test mode due to noise, the pattern length between each mode pins and v cc or v ss on the printed circuit board should be as shor t as possible, and th ey should be connected at low impedance. ? operation at start-up be sure to execute setting initialized reset (ini t) with initx pin immediately after start-up. immediately after that, also, hold the "l"-level input to th e initx pin for the stabilizatio n wait time required for the oscillator circuit to take the oscillati on stabilization wait time for the osc illator circuit and the stabilization wait time for the regulator (for init via the initx pin, the os cillation stabilization wait time setting is initialized to the minimum value). ? order of power turning on/off use the following procedure for turning the power on or off. if not using the a/d converter, connect avcc =vcc and avss = vss. turn on the po wer supply in the sequence vcc avcc avrh, and turn off the power in the reverse sequence.
mb91470/480 series 25 ? source oscillation input when turning on the power when turning the power on, maintain th e clock input until the device is rel eased from the oscillation stabilization wait state. ? cautions for operation during pll clock mode even if the oscillator comes off or the clock input st ops with the pll clock selected for mb91470/480 series, mb91470/480 series may continue to op erate at the free-run frequency of the pll?s internal self-oscillating oscillator circuit. performance of this operation , however, cannot be guaranteed. ? using an external clock when using an external clock, you must always input clock signals with oppo site phase from x0 pin to x1 pin simultaneously. however, as the x1 pin halts with an output at the "h" level during stop mode, insert a resistor of approximately 1 k ? externally to prevent a conflict between t he two outputs if using stop mode (oscillation stop mode). the figure below shows an example of how to use an external clock. ? c pin as mb91470/480 series includes an internal regulator, always connect a bypass capacitor of approximately 4.7 f to the c pin for use by the regulator. ? software reset on the synchronous mode be sure to meet the following two conditions before se tting 0 to the srst bit of stcr (standby control register) when the software reset is used on the synchronous mode. set the interrupt enable flag (i-flag) to interrupts disabled (i-flag=0). not used nmi x0 x1 mb91470/480 series ? example of using an external clock c 4.7 f gnd vss mb91470/480 series
mb91470/480 series 26 block diagram ? mb91470 series (144 pins) 3 2 16 3 2 3 2 md2 to md0 initx x0 x1 avcc10 av ss 10 avrh2 adtg2 an2-0 to an2-11 avrh 3 nmix int0 to int9 ain0 bin0 zin0 rto0 to rto5 dtti0 cki0 ic0 to ic 3 c tin0 to tin 3 tout0 to tout 3 ppg0 to ppg7 3 2 adtg 3 an 3 -0 to an 3 - 3 avrh4 adtg4 an4-0 to an4- 3 avcc12 av ss 12 gpio 16 s y s clk a15 to a00 d 3 1 to d16 a s x c s 0x to c s 2x rdy rdx wr0x, wr1x s ck0 to s ck5 s in0 to s in5 s ot0 to s ot5 vcc v ss fr60 cpu core watchdog timer bit search mac bus converter 32 ? 16 adapter interrupt controller 1 channel timing generator port i/f 1 channel up/down counter 2 channels reload timer 3 channels a/d activating compare 4 channels input capture 3 channels free-run timer 6 channels output compare 6 channels wave form generator 6 channels multi-function serial interface 1 + 10 channels external interrupt clock control 12 channels input 8/10-bit a/d converter 2 4 channels input 12-bit a/d converter 3 4 channels input 12-bit a/d converter 4 4 channels base timer -pwc -reload timer -pwm -ppg d-bus ram (max 28 kbytes) dmac 5 channels flash/rom (max 512 kbytes) f-bus ram (max 4 kbytes) 8 channels ppg multi-function timer down- conversion circuit 3 channels external bus i/f
mb91470/480 series 27 ? mb91480 series (100 pins) 3 2 16 3 2 3 2 md2 to md0 initx x0 x1 avcc10 av ss 10 avrh2 adtg2 an2-0 to an2-9 nmix int0 to int9 rto0 to rto11 dtti0,dtti1 cki0,cki1 ic0 to ic7 c tin0 to tin 3 tout0 to tout 3 ppg0 to ppg15 3 2 adtg0 an0-0 to an0- 3 adtg1 an1-0 to an1- 3 gpio 16 s ck0 to s ck2 s in0 to s in2 s ot0 to s ot2 vcc v ss clkpout fr60 cpu core watchdog timer bit search mac bus converter 32 ? 16 adapter interrupt controller 2 channel timing generator port i/f 2 channels reload timer 6 channels a/d activating compare 8 channels input capture 6 channels free-run timer 12 channels output compare 12 channels wave form generator 3 channels multi-function serial interface 1 + 10 channels external interrupt clock control 10 channels input 8/10-bit a/d converter 2 4 channels input 8/10-bit a/d converter 0 4 channels input 8/10-bit a/d converter 1 4 channels base timer -pwc -reload timer -pwm -ppg d-bus ram (max 28 kbytes) dmac 5 channels flash/rom (max 512 kbytes) f-bus ram (max 4 kbytes) 16 channels ppg multi-function timer down- conversion circuit clock monitor
mb91470/480 series 28 memory space 1. memory space the fr family has 4 gbytes of logical address space (2 32 addresses) available to the cpu by linear access. ? direct addressing areas the following address space ar eas are used as i/o areas. these areas are called direct addressing areas, in which the address of an operand can be specified directly by the instruction. the size of directly addressable areas depends on the length of the data being accessed as shown below. byte data access : 000 h to 0ff h half word data access : 000 h to 1ff h word data access : 000 h to 3ff h 2. memory map ? mb91470 series 0010 0000 h ffff ffff h i/o i/o 0020 0000 h 000 8 0000 h 0005 0000 h 0004 7000 h 0000 0000 h 0000 0400 h 000 3 f000 h 0001 0000 h 0004 0000 h i/o i/o i/o i/o f- bus ram 4 k b yte s acce ss prohi b ited f- bus ram 4 k b yte s acce ss prohi b ited f- bus ram 4 k b yte s acce ss prohi b ited single chip mode internal rom external bus mode external rom external bus mode access prohibited d-bus ram 28 kbytes 512 kbytes flash/rom access prohibited direct addressing area refer to ? i/o map? maximum value ? 12 kbytes : 00040000 h to 00042fff h ? 20 kbytes : 00040000 h to 00044fff h ? 28 kbytes : 00040000 h to 00046fff h maximum value ? 256 kbytes : 000c0000 h to 000fffff h ? 384 kbytes : 000a0000 h to 000fffff h ? 512 kbytes : 00080000 h to 000fffff h 144 pins 144 pins 144 pins access prohibited d-bus ram 28 kbytes 512 kbytes flash/rom external area access prohibited d-bus ram 28 kbytes external area access prohibited
mb91470/480 series 29 ? mb9480 series 0010 0000 h ffff ffff h i/o i/o 0020 0000 h 000 8 0000 h 0005 0000 h 0004 7000 h 0000 0000 h 0000 0400 h 000 3 f000 h 0001 0000 h 0004 0000 h single chip mode access prohibited access prohibited f-bus ram 4 kbytes d-bus ram 28 kbytes 512 kbytes flash/rom access prohibited direct addressing area refer to ? i/o map? maximum value ? 12 kbytes : 00040000 h to 00042fff h ? 28 kbytes : 00040000 h to 00046fff h maximum value ? 256 kbytes : 000c0000 h to 000fffff h ? 512 kbytes : 00080000 h to 000fffff h 100 pins
mb91470/480 series 30 mode settings the fr family uses mode pins (md2 to md0) and mode data to set the operation mode. 1. mode pins the md2 to md0 pins specify ho w the mode vector fetch and reset vector fetch is performed. settings other than those shown in the following table are prohibited. 2. mode data the data that is written to the internal mode register (modr) by the mode vector fetch is called mode data. after the mode register is set, the device runs in the operating mode specified by this register. the mode data is set by all of the reset sources. user programs cannot set the mode register.

[bit 23 to bit 19] reserved bits be sure to set these bits to ?00000 b ?. operation is not guaranteed if these bi ts are set to a value other than ?00000 b ?. [bit 18] roma (internal flash/rom enable bit) this bit configures whether the internal flash/rom area (8 0000 h to f ffff h ) is enabled. mode pins mode name reset vector access area remarks md2 md1 md0 0 0 0 internal rom mode vector internal 0 0 1 external rom mode vector external the bus width is set by mode register. roma function remarks 0 external rom mode internal flash/rom area (8 0000 h to f ffff h ) is used as an external area. 1 internal rom mode internal flash/rom area (8 0000 h to f ffff h ) is enabled. bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 0 0 0 0 0 roma wth1 wth0 operation mode setting bits
mb91470/480 series 31 [bit 17, bit 16] wth1, wth0 (b us width specification bit) these bits configure the bus width in external bus mode. in external bus mode, this value is set to the dbw1 and dbw0 bits of awr0 (cs0 area). 3. note the mode data set in the mode vector mu st be stored as byte data at 0x000ffff8 h . the data should be located in the highest byte from bit 31 to bit 24 bec ause the fr family uses big endian byte ordering. wth1 wth0 function remarks 0 0 8-bit bus width external bus mode 0 1 16-bit bus width external bus mode 10 ? (setting prohibited) 1 1 single chip mode single chip mode bit 31 24 23 16 15 8 7 0 incorrect 0x000ffff8 h xxxxxxxx xxxxxxxx xxxxxxxx mode data correct 0x000ffff8 h mode data xxxxxxxx xxxxxxxx xxxxxxxx 0x000ffffc h reset vector
mb91470/480 series 32 i/o map [how to read the table] note : initial values of register bits are represented as follows : ? 1 ? : initial value ? 1 ? ? 0 ? : initial value ? 0 ? ? x ? : initial value ? undefined ? ? - ? : no physical register at this location access to addresses where the data access pr operties have not been documented is prohibited. address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] b xxxxxxxx pdr1 [r/w] b xxxxxxxx pdr2 [r/w] b xxxxxxxx pdr3 [r/w] b xxxxxxxx t-unit port data register read/write attribute, access unit (b : byte, h : half word, w : word) initial value of register after reset register name (column 1 of the register is at address 4n, column 2 is at address 4 n + 1...) leftmost register address (for word -length access, column 1 of the register is the msb of the data.)
mb91470/480 series 33 (continued) address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] b, h, w xxxxxxxx pdr1 [r/w] b, h, w xxxxxxxx pdr2 [r/w] b, h, w xxxxxxxx pdr3 [r/w] b, h, w xxxxxxxx port data register 000004 h pdr5 [r/w] b, h, w -xxxxxxx pdr6 [r/w] b, h, w ------xx pdr8 [r/w] b, h, w xxxxxxxx pdr9 [r/w] b, h, w xxxxxxxx 000008 h pdra [r/w] b, h, w ---xxxxx pdrb [r/w] b, h, w xxxxxxxx pdrc [r/w] b, h, w xxxxxxxx pdrd [r/w] b, h, w ----xxxx 00000c h pdre [r/w] b, h, w xxxxxxxx pdrf [r/w] b, h, w xxxxxxxx pdrg [r/w] b, h, w --xxxxxx pdrh [r/w] b, h, w --xxxxxx 000010 h pdrj [r/w] b, h, w xxxxxxxx ? pdrl [r/w] b, h, w -----xxx pdrm [r/w] b, h, w ----xxxx 000014 h pdrp [r/w] b, h, w --xxxxxx pdrq [r/w] b, h, w --xxxxxx pdrr [r/w] b, h, w --xxxxxx pdrs [r/w] b, h, w --xxxxxx 000018 h to 00003c h ? (reserved) 000040 h eirr0 [r/w] b, h, w 00000000 enir0 [r/w] b, h, w 00000000 elvr0 [r/w] b, h, w 00000000 00000000 external interrupt (int0 to int7) 000044 h dicr [r/w] b, h, w -------0 hcrl [r/w, r] b, h, w 0--11111 ? delay interrupt/ hold request 000048 h tmrlr0 [w] h, w xxxxxxxx xxxxxxxx tmr0 [r] h, w xxxxxxxx xxxxxxxx reload timer 0 00004c h ? tmcsr0 [r/w, r] b, h, w ----00-- ---00000 000050 h tmrlr1 [w] h, w xxxxxxxx xxxxxxxx tmr1 [r] h, w xxxxxxxx xxxxxxxx reload timer 1 000054 h ? tmcsr1 [r/w, r] b, h, w ----00-- ---00000 000058 h to 00005c h ? (reserved)
mb91470/480 series 34 (continued) address register block + 0 + 1 + 2 + 3 000060 h ssr0 [r/w, r] b, h, w 00000011 escr0 [r/w]/ ibsr0 [r/w, r] b, h, w 00000000 scr0 [r/w] / ibcr0 [r/w, r] b, h, w 00000000 smr0 [r/w] b, h, w 000-0000 multi- function serial interface 0 000064 h bgr01[r/w] b, h, w 00000000 bgr00 [r/w] b, h, w 00000000 rdr0 [r]/ tdr0 [w]h, w -------0 00000000 rdr0 [r]/ tdr0 [w]h, w -------0 00000000 000068 h ? ismk0 [r/w] b, h, w 01111111 isba0 [r/w] b, h, w 00000000 00006c h fbyte02 [r/w] b, h, w 00000000 fbyte01 [r/w] b, h, w 00000000 fcr01 [r/w] b, h, w ---00100 fcr00 [r/w, r] b, h, w -0000000 000070 h ssr1 [r/w, r] b, h, w 00000011 escr1 [r/w]/ ibsr1 [r/w, r] b, h, w 00000000 scr1 [r/w] / ibcr1 [r/w, r] b, h, w 00000000 smr1 [r/w] b, h, w 000-0000 multi- function serial interface 1 000074 h bgr11 [r/w] b, h, w 00000000 bgr10 [r/w] b, h, w 00000000 rdr1 [r]/ tdr1 [w]h, w -------0 00000000 rdr1 [r]/ tdr1 [w]h, w -------0 00000000 000078 h ? ismk1 [r/w] b, h, w 01111111 isba1 [r/w] b, h, w 00000000 00007c h fbyte21 [r/w] b, h, w 00000000 fbyte11 [r/w] b, h, w 00000000 fcr11 [r/w] b, h, w ---00100 fcr10 [r/w, r] b, h, w -0000000 000080 h ssr2 [r/w, r] b, h, w 00000011 escr2 [r/w]/ ibsr2 [r/w, r] b, h, w 00000000 scr2 [r/w] / ibcr2 [r/w, r] b, h, w 00000000 smr2 [r/w] b, h, w 000-0000 multi- function serial interface 2 000084 h bgr21 [r/w] b, h, w 00000000 bgr20 [r/w] b, h, w 00000000 rdr2 [r]/ tdr2 [w]h, w -------0 00000000 rdr2 [r]/ tdr2 [w]h, w -------0 00000000 000088 h ? ismk2 [r/w] b, h, w 01111111 isba2 [r/w] b, h, w 00000000 00008c h fbyte22 [r/w] b, h, w 00000000 fbyte21 [r/w] b, h, w 00000000 fcr21 [r/w] b, h, w ---00100 fcr20 [r/w, r] b, h, w -0000000
mb91470/480 series 35 (continued) address register block + 0 + 1 + 2 + 3 000090 h ssr3 [r/w, r] b, h, w 00000011 escr3 [r/w]/ ibsr3 [r/w, r] b, h, w 00000000 scr3 [r/w] / ibcr3 [r/w, r] b, h, w 00000000 smr3 [r/w] b, h, w 000-0000 multi- function serial interface 3 000094 h bgr31 [r/w] b, h, w 00000000 bgr30 [r/w] b, h, w 00000000 rdr3 [r]/ tdr3 [w]h, w -------0 00000000 rdr3 [r]/ tdr3 [w]h, w -------0 00000000 000098 h ? ismk3 [r/w] b, h, w 01111111 isba3 [r/w] b, h, w 00000000 00009c h fbyte32 [r/w] b, h, w 00000000 fbyte31 [r/w] b, h, w 00000000 fcr31 [r/w] b, h, w ---00100 fcr30 [r/w, r] b, h, w -0000000 0000a0 h occpbh0, occpbl0 [w]/ occph0, occpl0 [r] h, w 00000000 00000000 occpbh1, occpbl1 [w]/ occph1, occpl1 [r] h, w 00000000 00000000 ocu0 0000a4 h occpbh2, occpbl2 [w]/ occph2, occpl2 [r] h, w 00000000 00000000 occpbh3, occpbl3 [w]/ occph3, occpl3 [r] h, w 00000000 00000000 0000a8 h occpbh4, occpbl4 [w]/ occph4, occpl4 [r] h, w 00000000 00000000 occpbh5, occpbl5 [w]/ occph5, occpl5 [r] h, w 00000000 00000000 0000ac h ocsh1 [r/w] b, h, w -1100000 ocsl0 [r/w] b, h, w 00001100 ocsh3 [r/w] b, h, w -1100000 ocsl2 [r/w] b, h, w 00001100 0000b0 h ocsh5 [r/w] b, h, w -1100000 ocsl4 [r/w] b, h, w 00001100 ocmod0 [r/w] b, h, w --000000 ? 0000b4 h cpclrbh0, cpclrbl0 [w]/ cpclrh0, cpclrl0 [r] h, w 11111111 11111111 tcdth0, tcdtl0 [r/w] h, w 00000000 00000000 free-run timer 0 0000b8 h tccsh0 [r/w] b, h, w 00000000 tccsl0 [r/w] b, h, w 01000000 tccsm0 [r/w] b, h, w ----0000 adtrgc0 [r/w] b, h, w -000-000 0000bc h cpclrbh1, cpclrbl1 [w] / cpclrh1, cpclrl1 [r] h, w 11111111 11111111 tcdth1, tcdtl1 [r/w] h, w 00000000 00000000 free-run timer 1 0000c0 h tccsh1 [r/w] b, h, w 00000000 tccsl1 [r/w] b, h, w 01000000 tccsm1 [r/w] b, h, w ----0000 adtrgc1 [r/w] b, h, w -000-000
mb91470/480 series 36 (continued) address register block + 0 + 1 + 2 + 3 0000c4 h cpclrbh2, cpclrbl2 [w] / cpclrh2, cpclrl2 [r] h, w 11111111 11111111 tcdth2, tcdtl2 [r/w] h, w 00000000 00000000 free-run timer 2 0000c8 h tccsh2 [r/w] b, h, w 00000000 tccsl2 [r/w] b, h, w 01000000 tccsm2 [r/w] b, h, w ----0000 adtrgc2 [r/w] b, h, w -000-000 0000cc h ? frs2 [r/w] b, h, w -000-000 frs1 [r/w] b, h, w -000-000 frs0 [r/w] b, h, w -000-000 free-run timer selector 0 0000d0 h ? frs4 [r/w] b, h, w -000-000 frs3 [r/w] b, h, w -000-000 0000d4 h ipcph0, ipcpl0 [r] h, w xxxxxxxx xxxxxxxx ipcph1, ipcpl1 [r] h, w xxxxxxxx xxxxxxxx icu0 0000d8 h ipcph2, ipcpl2 [r] h, w xxxxxxxx xxxxxxxx ipcph3, ipcpl3 [r] h, w xxxxxxxx xxxxxxxx 0000dc h picsh01 [w, r] b, h, w 00000000 picsl01 [r/w] b, h, w 00000000 icsh23 [r] b, h, w ------00 icsl23[r/w] b, h, w 00000000 0000e0 h tmrrh0, tmrrl0 [r/w] h, w xxxxxxxx xxxxxxxx tmrrh1, tmrrl1 [r/w] h, w xxxxxxxx xxxxxxxx wave form generator 0 0000e4 h tmrrh2, tmrrl2 [r/w] h, w xxxxxxxx xxxxxxxx ? 0000e8 h dtcr0 [r/w] b, h, w 00000000 dtcr1 [r/w] b, h, w 00000000 dtcr2 [r/w] b, h, w 00000000 ? 0000ec h ? sigcr10 [r/w] b, h, w 00000000 ? sigcr20 [r/w] b, h, w 000000-1 0000f0 h adcomp0 [w]/ adcompb0 [r] h, w 00000000 00000000 adcompd0 [w]/ adcompdb0 [r] h, w 00000000 00000000 a/d activating compare 0 0000f4 h adcomp1 [w]/ adcompb1 [r] h, w 00000000 00000000 adcompd1 [w]/ adcompdb1 [r] h, w 00000000 00000000 0000f8 h adcomp2 [w]/ adcompb2 [r] h, w 00000000 00000000 adcompd2 [w]/ adcompdb2 [r] h, w 00000000 00000000 0000fc h ? adtgbuf0 [r/w] b, h, w -000-111 adtgsel0 [r/w] b, h, w --000000 adtgce0 [r/w] b, h, w --000000
mb91470/480 series 37 (continued) address register block + 0 + 1 + 2 + 3 000100 h prlh0 [r/w] b, h, w xxxxxxxx prll0 [r/w] b, h, w xxxxxxxx prlh1 [r/w] b, h, w xxxxxxxx prll1 [r/w] b, h, w xxxxxxxx ppg 000104 h prlh2 [r/w] b, h, w xxxxxxxx prll2 [r/w] b, h, w xxxxxxxx prlh3 [r/w] b, h, w xxxxxxxx prll3 [r/w] b, h, w xxxxxxxx 000108 h ppgc0 [r/w] b, h, w 00000000 ppgc1 [r/w] b, h, w 00000000 ppgc2 [r/w] b, h, w 00000000 ppgc3 [r/w] b, h, w 00000000 00010c h prlh4 [r/w] b, h, w xxxxxxxx prll4 [r/w] b, h, w xxxxxxxx prlh5 [r/w] b, h, w xxxxxxxx prll5 [r/w] b, h, w xxxxxxxx 000110 h prlh6 [r/w] b, h, w xxxxxxxx prll6 [r/w] b, h, w xxxxxxxx prlh7 [r/w] b, h, w xxxxxxxx prll7 [r/w] b, h, w xxxxxxxx 000114 h ppgc4 [r/w] b, h, w 00000000 ppgc5 [r/w] b, h, w 00000000 ppgc6 [r/w] b, h, w 00000000 ppgc7 [r/w] b, h, w 00000000 000118 h prlh8 [r/w] b, h, w xxxxxxxx prll8 [r/w] b, h, w xxxxxxxx prlh9 [r/w] b, h, w xxxxxxxx prll9 [r/w] b, h, w xxxxxxxx 00011c h prlh10 [r/w] b, h, w xxxxxxxx prll10 [r/w] b, h, w xxxxxxxx prlh11 [r/w] b, h, w xxxxxxxx prll11 [r/w] b, h, w xxxxxxxx 000120 h ppgc8 [r/w] b, h, w 00000000 ppgc9 [r/w] b, h, w 00000000 ppgc10 [r/w] b, h, w 00000000 ppgc11 [r/w] b, h, w 00000000 000124 h prlh12 [r/w] b, h, w xxxxxxxx prll12 [r/w] b, h, w xxxxxxxx prlh13 [r/w] b, h, w xxxxxxxx prll13 [r/w] b, h, w xxxxxxxx 000128 h prlh14 [r/w] b, h, w xxxxxxxx prll14 [r/w] b, h, w xxxxxxxx prlh15 [r/w] b, h, w xxxxxxxx prll15 [r/w] b, h, w xxxxxxxx 00012c h ppgc12 [r/w] b, h, w 00000000 ppgc13 [r/w] b, h, w 00000000 ppgc14 [r/w] b, h, w 00000000 ppgc15 [r/w] b, h, w 00000000 000130 h trg [r/w] b, h 00000000 00000000 ? gatec0 [r/w] b --00--00 000134 h revc [r/w] b, h 00000000 00000000 ? gatec4 [r/w] b ------00 000138 h ? gatec8 [r/w] b --00--00
mb91470/480 series 38 (continued) address register block + 0 + 1 + 2 + 3 00013c h ? gatec12 [r/w] b ------00 ppg 000140 h ? (reserved) 000144 h ttcr0 [r/w, w, r] b, h, w 11110000 ? timing generator 0 000148 h comp0 [r/w] b, h, w 00000000 comp2 [r/w] b, h, w 00000000 comp4 [r/w] b, h, w 00000000 comp6 [r/w] b, h, w 00000000 00014c h ttcr1 [r/w, w, r] b, h, w 11110000 ? timing generator 1 000150 h comp1 [r/w] b, h, w 00000000 comp3 [r/w] b, h, w 00000000 comp5 [r/w] b, h, w 00000000 comp7 [r/w] b, h, w 00000000 000154 h eirr1 [r/w] b, h, w 00000000 enir1 [r/w] b, h, w 00000000 elvr1 [r/w] b, h, w 00000000 00000000 external interrupt (int8 to int15) 000158 h ? (reserved) 00015c h ? cmclkr [r/w] b ----0000 clock monitor 000160 h bt0tmr [r] b, h, w 00000000 00000000 bt0tmcr [r/w] b, h, w 00000000 00000000 base timer 0 000164 h ? bt0stc [r/w] b 00000000 ? 000168 h bt0pcsr/bt0prll [r/w] h, w xxxxxxxx xxxxxxxx bt0pdut/bt0prlh/bt0dtbf [r/w] h, w xxxxxxxx xxxxxxxx 00016c h ? (reserved) 000170 h aicr2 [r/w] b, h, w ----1111 11111111 ? 8/10-bit a/d converter 2 (12 channels) 000174 h adcs2 [r/w, w] b, h, w 0000000- ? adch2 [r/w] b, h, w 00000000 admd2 [r/w] b, h, w 00001111 000178 h adcd002 [r] b, h, w 10----xx xxxxxxxx adcd012 [r] b, h, w 10----xx xxxxxxxx 00017c h adcd022 [r] b, h, w 10----xx xxxxxxxx adcd032 [r] b, h, w 10----xx xxxxxxxx
mb91470/480 series 39 (continued) address register block + 0 + 1 + 2 + 3 000180 h adcd042 [r] b, h, w 10----xx xxxxxxxx adcd052 [r] b, h, w 10----xx xxxxxxxx 8/10-bit a/d converter 2 (12 channels) 000184 h adcd062 [r] b, h, w 10----xx xxxxxxxx adcd072 [r] b, h, w 10----xx xxxxxxxx 000188 h adcd082 [r] b, h, w 10----xx xxxxxxxx adcd092 [r] b, h, w 10----xx xxxxxxxx 00018c h adcd102 [r] b, h, w 10----xx xxxxxxxx adcd112 [r] b, h, w 10----xx xxxxxxxx 000190 h ? (reserved) 000194 h ? (reserved) 000198 h ? (reserved) 00019c h ? (reserved) 0001a0 h occpbh6, occpbl6 [w]/ occph6, occpl6 [r] h, w 00000000 00000000 occpbh7, occpbl7 [w]/ occph7, occpl7 [r] h, w 00000000 00000000 ocu1 0001a4 h occpbh8, occpbl8 [w]/ occph8, occpl8 [r] h, w 00000000 00000000 occpbh9, occpbl9 [w]/ occph9, occpl9 [r] h, w 00000000 00000000 0001a8 h occpbh10, occpbl10 [w]/ occph10, occpl10 [r] h, w 00000000 00000000 occpbh11, occpbl11 [w]/ occph11, occpl11 [r] h, w 00000000 00000000 0001ac h ocsh7 [r/w] b, h, w -1100000 ocsl6 [r/w] b, h, w 00001100 ocsh9 [r/w] b, h, w -1100000 ocsl8 [r/w] b, h, w 00001100 0001b0 h ocsh11 [r/w] b, h, w -1100000 ocsl10 [r/w] b, h, w 00001100 ocmod1 [r/w] b, h, w --000000 ? 0001b4 h cpclrbh3, cpclrbl3 [w]/ cpclrh3, cpclrl3 [r] h, w 11111111 11111111 tcdth3, tcdtl3 [r/w] h, w 00000000 00000000 free-run timer 3 0001b8 h tccsh3 [r/w] b, h, w 00000000 tccsl3 [r/w] b, h, w 01000000 tccsm3 [r/w] b, h, w ----0000 adtrgc3 [r/w] b, h, w -000-000 0001bc h cpclrbh4, cpclrbl4 [w] / cpclrh4, cpclrl4 [r] h, w 11111111 11111111 tcdth4, tcdtl4 [r/w] h, w 00000000 00000000 free-run timer 4 0001c0 h tccsh4 [r/w] b, h, w 00000000 tccsl4 [r/w] b, h, w 01000000 tccsm4 [r/w] b, h, w ----0000 adtrgc4 [r/w] b, h, w -000-000
mb91470/480 series 40 (continued) address register block + 0 + 1 + 2 + 3 0001c4 h cpclrbh5, cpclrbl5 [w] / cpclrh5, cpclrl 5 [r] h, w 11111111 11111111 tcdth5, tcdtl5 [r/w] h, w 00000000 00000000 free-run timer 5 0001c8 h tccsh5 [r/w] b, h, w 00000000 tccsl5 [r/w] b, h, w 01000000 tccsm5 [r/w] b, h, w ----0000 adtrgc5 [r/w] b, h, w -000-000 0001cc h ? frs7 [r/w] b, h, w -011-011 frs6 [r/w] b, h, w -011-011 frs5 [r/w] b, h, w -011-011 free-run timer selector 1 0001d0 h ? frs9 [r/w] b, h, w -011-011 frs8 [r/w] b, h, w -011-011 0001d4 h ipcph4, ipcpl4 [r] h, w xxxxxxxx xxxxxxxx ipcph5, ipcpl5 [r] h, w xxxxxxxx xxxxxxxx icu1 0001d8 h ipcph6, ipcpl6 [r] h, w xxxxxxxx xxxxxxxx ipcph7, ipcpl7 [r] h, w xxxxxxxx xxxxxxxx 0001dc h picsh45 [w, r] b, h, w 00000000 picsl45 [r/w] b, h, w 00000000 icsh67 [r] b, h, w ------00 icsl67 [r/w] b, h, w 00000000 0001e0 h tmrrh3, tmrrl3 [r/w] h, w xxxxxxxx xxxxxxxx tmrrh4, tmrrl4 [r/w] h, w xxxxxxxx xxxxxxxx wave form generator 1 0001e4 h tmrrh5, tmrrl5 [r/w] h, w xxxxxxxx xxxxxxxx ? 0001e8 h dtcr3 [r/w] b, h, w 00000000 dtcr4 [r/w] b, h, w 00000000 dtcr5 [r/w] b, h, w 00000000 ? 0001ec h ? sigcr11 [r/w] b, h, w 00000000 ? sigcr21 [r/w] b, h, w 000000-1 0001f0 h adcomp3 [w]/ adcompb3 [r] h, w 00000000 00000000 adcompd3 [w]/ adcompdb3 [r] h, w 00000000 00000000 a/d activating compare 1 0001f4 h adcomp4 [w]/ adcompb4 [r] h, w 00000000 00000000 adcompd4 [w]/ adcompdb4 [r] h, w 00000000 00000000 0001f8 h adcomp5 [w]/ adcompb5 [r] h, w 00000000 00000000 adcompd5 [w]/ adcompdb5 [r] h, w 00000000 00000000 0001fc h ? adtgbuf1 [r/w] b, h, w -000-111 adtgsel1 [r/w] b, h, w --000000 adtgce1[r/w] b, h, w --000000
mb91470/480 series 41 (continued) address register block + 0 + 1 + 2 + 3 000200 h dmaca0 [r/w] b, h, w * 1 00000000 ----xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000208 h dmaca1 [r/w] b, h, w * 1 00000000 ----xxxx xxxxxxxx xxxxxxxx 00020c h dmacb1 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000210 h dmaca2 [r/w] b, h, w * 1 00000000 ----xxxx xxxxxxxx xxxxxxxx 000214 h dmacb2 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000218 h dmaca3 [r/w] b, h, w * 1 000000000 ----xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000220 h dmaca4 [r/w] b, h, w * 1 00000000 ----xxxx xxxxxxxx xxxxxxxx 000224 h dmacb4 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000228 h to 00023c h ? (reserved) 000240 h dmacr [r/w] b, h, w 0--00000 -------- -------- -------- dmac 000244 h to 00039c h ? (reserved) 0003a0 h dsp-pc [r/w] b, h, w 000000-0 dsp-csr [r/w, r, w] b, h, w 00000000 ? mac 0003a4 h dsp-ly [r/w], w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003a8 h dsp-ot0 [r], w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003ac h dsp-ot1 [r], w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003b0 h dsp-ot2 [r], w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003b4 h dsp-ot3 [r], w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91470/480 series 42 (continued) address register block + 0 + 1 + 2 + 3 0003b8 h dsp-ot4 [r], w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx mac 0003bc h dsp-ot5 [r], w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003c0 h dsp-ot6 [r], w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003c4 h dsp-ot7 [r], w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003c8 h dsp-ac0 [r], w -------- -------- -------- 00000000 0003cc h dsp-ac1 [r], w 00000000 00000000 00000000 00000000 0003d0 h dsp-ac2 [r], w 00000000 00000000 00000000 00000000 0003d4 h to 0003ec h ? (reserved) 0003f0 h bsd0 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h ddr0 [r/w] b, h, w 00000000 ddr1 [r/w] b, h, w 00000000 ddr2 [r/w] b, h, w 00000000 ddr3 [r/w] b, h, w 00000000 port direction register 000404 h ddr5 [r/w] b, h, w -0000000 ddr6 [r/w] b, h, w ------00 ddr8 [r/w] b, h, w 00000000 ddr9 [r/w] b, h, w 00000000 000408 h ddra [r/w] b, h, w ---00000 ddrb [r/w] b, h, w 00000000 ddrc [r/w] b, h, w 00000000 ddrd [r/w] b, h, w ----0000 00040c h ddre [r/w] b, h, w 00000000 ddrf [r/w] b, h, w 00000000 ddrg [r/w] b, h, w --000000 ddrh [r/w] b, h, w --000000 000410 h ddrj [r/w] b, h, w 00000000 ? ddrl [r/w] b, h, w -----000 ddrm [r/w] b, h, w ----0000
mb91470/480 series 43 (continued) address register block + 0 + 1 + 2 + 3 000414 h ddrp [r/w] b, h, w --000000 ddrq [r/w] b, h, w --000000 ddrr [r/w] b, h, w --000000 ddrs [r/w] b, h, w --000000 port direction register 000418 h ? (reserved) 00041c h ? (reserved) 000420 h pfr0 [r/w] b, h, w 11111111 pfr1 [r/w] b, h, w 11111111 pfr2 [r/w] b, h, w 11111111 pfr3 [r/w] b, h, w 11111111 port function register 000424 h pfr5 [r/w] b, h, w -1111111 pfr6 [r/w] b, h, w ------11 pfr8 [r/w] b, h, w 0000---- pfr9 [r/w] b, h, w 00000000 000428 h ?? pfrc [r/w] b, h, w --0-00-0 ? 00042c h ? pfrf [r/w] b, h, w -------0 pfrg [r/w] b, h, w --0-00-0 pfrh [r/w] b, h, w --0-00-0 000430 h pfrj [r/w] b, h, w 0-0-0-0- ? pfrm [r/w] b, h, w ----0000 000434 h ? pfrq [r/w] b, h, w --000000 ? pfrs [r/w] b, h, w --000000 000438 h ? (reserved) 00043c h ? (reserved) 000440 h icr00 [r/w, r] b, h, w ---11111 icr01 [r/w, r] b, h, w ---11111 icr02 [r/w, r] b, h, w ---11111 icr03 [r/w, r] b, h, w ---11111 interrupt controller 000444 h icr04 [r/w, r] b, h, w ---11111 icr05 [r/w, r] b, h, w ---11111 icr06 [r/w, r] b, h, w ---11111 icr07 [r/w, r] b, h, w ---11111 000448 h icr08 [r/w, r] b, h, w ---11111 icr09 [r/w, r] b, h, w ---11111 icr10 [r/w, r] b, h, w ---11111 icr11 [r/w, r] b, h, w ---11111 00044c h icr12 [r/w, r] b, h, w ---11111 icr13 [r/w, r] b, h, w ---11111 icr14 [r/w, r] b, h, w ---11111 icr15 [r/w, r] b, h, w ---11111 000450 h icr16 [r/w, r] b, h, w ---11111 icr17 [r/w, r] b, h, w ---11111 icr18 [r/w, r] b, h, w ---11111 icr19 [r/w, r] b, h, w ---11111 000454 h icr20 [r/w, r] b, h, w ---11111 icr21 [r/w, r] b, h, w ---11111 icr22 [r/w, r] b, h, w ---11111 icr23 [r/w, r] b, h, w ---11111
mb91470/480 series 44 (continued) address register block + 0 + 1 + 2 + 3 000458 h icr24 [r/w, r] b, h, w ---11111 icr25 [r/w, r] b, h, w ---11111 icr26 [r/w, r] b, h, w ---11111 icr27 [r/w, r] b, h, w ---11111 interrupt controller 00045c h icr28 [r/w, r] b, h, w ---11111 icr29 [r/w, r] b, h, w ---11111 icr30 [r/w, r] b, h, w ---11111 icr31 [r/w, r] b, h, w ---11111 000460 h icr32 [r/w, r] b, h, w ---11111 icr33 [r/w, r] b, h, w ---11111 icr34 [r/w, r] b, h, w ---11111 icr35 [r/w, r] b, h, w ---11111 000464 h icr36 [r/w, r] b, h, w ---11111 icr37 [r/w, r] b, h, w ---11111 icr38 [r/w, r] b, h, w ---11111 icr39 [r/w, r] b, h, w ---11111 000468 h icr40 [r/w, r] b, h, w ---11111 icr41 [r/w, r] b, h, w ---11111 icr42 [r/w, r] b, h, w ---11111 icr43 [r/w, r] b, h, w ---11111 00046c h icr44 [r/w, r] b, h, w ---11111 icr45 [r/w, r] b, h, w ---11111 icr46 [r/w, r] b, h, w ---11111 icr47 [r/w, r] b, h, w ---11111 000470 h to 00047c h ? (reserved) 000480 h rsrr [r/w] b, h, w 1-0-0-00 stcr [r/w] b, h, w 001100-1 tbcr [r/w] b, h, w 00xxx-00 ctbr [w] b, h, w xxxxxxxx clock control block 000484 h clkr [r/w] b, h, w -000-000 ? divr0 [r/w] b, h, w 00000011 divr1 [r/w] b, h, w 00000000 000488 h to 0004fc h ? (reserved) 000500 h ? aicr0 [r/w] b, h, w ----1111 ? 8/10-bit a/d converter 0 (4 channels) 000504 h adcs0 [r/w, w] b, h, w 0000000- ? adch0 [r/w] b, h, w --00--00 admd0 [r/w] b, h, w 00001111 000508 h adcd000 [r] b, h, w 10----xx xxxxxxxx adcd010 [r] b, h, w 10----xx xxxxxxxx 00050c h adcd020 [r] b, h, w 10----xx xxxxxxxx adcd030 [r] b, h, w 10----xx xxxxxxxx
mb91470/480 series 45 (continued) address register block + 0 + 1 + 2 + 3 000510 h ? aicr1 [r/w] b, h, w ----1111 ? 8/10-bit a/d converter 1 (4 channels) 000514 h adcs1 [r/w, w] b, h, w 0000000- ? adch1 [r/w] b, h, w --00--00 admd1 [r/w] b, h, w 00001111 000518 h adcd001 [r] b, h, w 10----xx xxxxxxxx adcd011 [r] b, h, w 10----xx xxxxxxxx 00051c h adcd021 [r] b, h, w 10----xx xxxxxxxx adcd031 [r] b, h, w 10----xx xxxxxxxx 000520 h ? aicr3 [r/w] b, h, w ----1111 ? 12-bit a/d converter 3 (4 channels) 000524 h adcs3 [r/w, w] b, h, w 0000000- ? adch3 [r/w] b, h, w --00--00 admd3 [r/w] b, h, w 00001111 000528 h adcd003 [r] b, h, w 10--xxxx xxxxxxxx adcd013 [r] b, h, w 10--xxxx xxxxxxxx 00052c h adcd023 [r] b, h, w 10--xxxx xxxxxxxx adcd033 [r] b, h, w 10--xxxx xxxxxxxx 000530 h ? aicr4 [r/w] b, h, w ----1111 ? 12-bit a/d converter 4 (4 channels) 000534 h adcs4 [r/w, w] b, h, w 0000000- ? adch4 [r/w] b, h, w --00--00 admd4 [r/w] b, h, w 00001111 000538 h adcd004 [r] b, h, w 10--xxxx xxxxxxxx adcd014 [r] b, h, w 10--xxxx xxxxxxxx 00053c h adcd024 [r] b, h, w 10--xxxx xxxxxxxx adcd034 [r] b, h, w 10--xxxx xxxxxxxx 000540 h rcr10 [w] b, h, w xxxxxxxx rcr00 [w] b, h, w xxxxxxxx udcr10 [r] b, h, w 00000000 udcr00 [r] b, h, w 00000000 up/down counter 0 000544 h ccrh0 [r/w] b, h, w 00000000 ccrl0 [r/w, r] b, h, w -0001000 ? csr0 [r/w, r] b, h, w 00000000 000548 h to 00055c h ? (reserved)
mb91470/480 series 46 (continued) address register block + 0 + 1 + 2 + 3 000560 h ssr4 [r/w, r] b, h, w 00000011 escr4 [r/w]/ ibsr4 [r/w, r] b, h, w 00000000 scr4 [r/w] / ibcr4 [r/w, r] b, h, w 00000000 smr4 [r/w] b, h, w 000-0000 multi- function serial interface 4 000564 h bgr41 [r/w] b, h, w 00000000 bgr40 [r/w] b, h, w 00000000 rdr4 [r]/tdr4 [w]h, w -------0 00000000 000568 h ? ismk4 [r/w] b, h, w 01111111 isba4 [r/w] b, h, w 00000000 00056c h fbyte42 [r/w] b, h, w 00000000 fbyte41 [r/w] b, h, w 00000000 fcr41 [r/w] b, h, w ---00100 fcr40 [r/w, r] b, h, w -0000000 000570 h ssr5 [r/w, r] b, h, w 00000011 escr5 [r/w]/ ibsr5 [r/w, r] b, h, w 00000000 scr5 [r/w] / ibcr5 [r/w, r] b, h, w 00000000 smr5 [r/w] b, h, w 000-0000 multi- function serial interface 5 000574 h bgr51 [r/w] b, h, w 00000000 bgr50 [r/w] b, h, w 00000000 rdr5 [r]/tdr5 [w]h, w -------0 00000000 000578 h ? ismk5 [r/w] b, h, w 01111111 isba5 [r/w] b, h, w 00000000 00057c h fbyte52 [r/w] b, h, w 00000000 fbyte51 [r/w] b, h, w 00000000 fcr51 [r/w] b, h, w ---00100 fcr50 [r/w, r] b, h, w -0000000 000580 h bt1tmr [r] b, h, w 00000000 00000000 bt1tmcr [r/w] b, h, w 00000000 00000000 base timer 1 000584 h ? bt1stc [r/w] b 00000000 ? 000588 h bt1pcsr/bt1prll [r/w] h, w xxxxxxxx xxxxxxxx bt1pdut/bt1prlh/bt1dtbf [r/w] h, w xxxxxxxx xxxxxxxx 00058c h ? (reserved) 000590 h bt2tmr [r] b, h, w 00000000 00000000 bt2tmcr [r/w] b, h, w 00000000 00000000 base timer 2 000594 h ? bt2stc [r/w] b 00000000 ? 000598 h bt2pcsr/bt2prll [r/w] h, w xxxxxxxx xxxxxxxx bt2pdut/bt2prlh/bt2dtbf [r/w] h, w xxxxxxxx xxxxxxxx 00059c h ? (reserved)
mb91470/480 series 47 (continued) address register block + 0 + 1 + 2 + 3 0005a0 h bt3tmr [r] b, h, w 00000000 00000000 bt3tmcr [r/w] b, h, w 00000000 00000000 base timer 3 0005a4 h ? bt3stc [r/w] b 00000000 ? 0005a8 h bt3pcsr/bt3prll [r/w] h, w xxxxxxxx xxxxxxxx bt3pdut/bt3prlh/bt3dtbf [r/w] h, w xxxxxxxx xxxxxxxx 0005ac h ? (reserved) 0005b0 h to 0005fc h ? (reserved) 000600 h pcr0 [r/w] b, h, w 00000000 pcr1 [r/w] b, h, w 00000000 pcr2 [r/w] b, h, w 00000000 pcr3 [r/w] b, h, w 00000000 pull-up resistor control register 000604 h pcr5 [r/w] b, h, w -0000000 pcr6 [r/w] b, h, w ------00 pcr8 [r/w] b, h, w 00000000 pcr9 [r/w] b, h, w 00000000 000608 h pcra [r/w] b, h, w ---00000 pcrb [r/w] b, h, w 00000000 pcrc [r/w] b, h, w 00000000 pcrd [r/w] b, h, w ----0000 00060c h pcre [r/w] b, h, w 00000000 pcrf [r/w] b, h, w 00000000 pcrg [r/w] b, h, w --000000 pcrh [r/w] b, h, w --000000 000610 h pcrj [r/w] b, h, w 00000000 ? pcrl [r/w] b, h, w -----000 pcrm [r/w] b, h, w ----0000 000614 h pcrp [r/w] b, h, w --000000 pcrq [r/w] b, h, w --000000 pcrr [r/w] b, h, w --000000 pcrs [r/w] b, h, w --000000 000618 h to 00063c h ? (reserved) 000640 h asr0 [r/w] h, w 00000000 00000000 * 2 acr0 [r/w] h, w 1111xx-- --000000 * 2 external bus interface 000644 h asr1 [r/w] h, w xxxxxxxx xxxxxxxx * 2 acr1 [r/w] h, w xxxxxx-- --xxxxxx * 2 000648 h asr2 [r/w] h, w xxxxxxxx xxxxxxxx * 2 acr2 [r/w] h, w xxxxxx-- --xxxxxx * 2 00064c h ?
mb91470/480 series 48 (continued) address register block + 0 + 1 + 2 + 3 000650 h ? external bus interface 000654 h ? 000658 h ? 00065c h ? 000660 h awr0 [r/w] h, w 0111---- 1111-111 * 2 awr1 [r/w] h, w xxxx---- xxxx-xxx * 2 000664 h awr2 [r/w] h, w xxxx---- xxxx-xxx * 2 ? 000668 h ? 00066c h ? 000670 h ? 000674 h ? 000678 h ? 00067c h ? 000680 h cser [r/w] b, h -----001 ? 000684 h to 0007f8 h ? (reserved) 0007fc h ? modr [w] xxxxxxxx ? mode register 000800 h to 000ffc h ? (reserved) 001000 h dmasa0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001004 h dmada0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001008 h dmasa1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00100c h dmada1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001010 h dmasa2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001014 h dmada2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001018 h dmasa3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91470/480 series 49 (continued) address register block + 0 + 1 + 2 + 3 00101c h dmada3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001020 h dmasa4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001024 h dmada4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001028 h to 006ffc h ? (reserved) 007000 h flcr [r/w, r] b ----x-0- ? flash memory 007004 h flwc [r/w] b --11-011 ? 007008 h ? 00700c h ? 007010 h ? 007014 h to 00701c h ? (reserved) 007020 h wren [r/w] h 00000000 00000000 ? wild register control block 007024 h ? 007028 h ? 00702c h ? 007030 h wa00 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 007034 h wd00 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007038 h wa01 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 00703c h wd01 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007040 h wa02 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 007044 h wd02 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007048 h wa03 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 00704c h wd03 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91470/480 series 50 (continued) address register block + 0 + 1 + 2 + 3 007050 h wa04 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- wild register control block 007054 h wd04 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007058 h wa05 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 00705c h wd05 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007060 h wa06 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 007064 h wd06 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007068 h wa07 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 00706c h wd07 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007070 h wa08 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 007074 h wd08 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007078 h wa09 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 00707c h wd09 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007080 h wa10 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 007084 h wd10 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007088 h wa11 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 00708c h wd11 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007090 h wa12 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 007094 h wd12 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007098 h wa13 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 00709c h wd13 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91470/480 series 51 (continued) *1 : the lower 16 bits (dtc15 to dtc0) of dmaca0 to dmaca4 cannot be accessed as bytes. *2 : register whose initial value depends on the rese t level. the initial values shown are for initx = ?l?. notes : ? data is undefined in reserved or ( ? ) area. ? do not execute read modify write (rmw) in struction on registers having a write-only bit. ? the initial values are varied depending on the product series. please refer to the hardware manual of mb91470/480 for more details. address register block + 0 + 1 + 2 + 3 0070a0 h wa14 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- wild register control block 0070a4 h wd14 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0070a8 h wa15 [r/w] w -------- ----xxxx xxxxxxxx xxxxxx-- 0070ac h wd15 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0070b0 h to 00bffc h ? (reserved) 00c000 h to 00c0fc h x-ram (coefficient ram) [r/w] 64 32-bit mac 00c100 h to 00c1fc h y-ram (variable ram) [r/w] 64 32-bit 00c200 h to 00c3fc h i-ram (instruction ram) [r/w] 128 32-bit 00c400 h to 00fffc h ? (reserved) 010000 h to 0ffffc h ? (reserved)
mb91470/480 series 52 interrupt vector (continued) interrupt source interrupt number interrupt level offset tbr default address decimal hexa- decimal reset 0 00 ? 3fc h 000ffffc h mode vector 1 01 ? 3f8 h 000ffff8 h system reserved 2 02 ? 3f4 h 000ffff4 h system reserved 3 03 ? 3f0 h 000ffff0 h system reserved 4 04 ? 3ec h 000fffec h system reserved 5 05 ? 3e8 h 000fffe8 h system reserved 6 06 ? 3e4 h 000fffe4 h coprocessor absent trap 7 07 ? 3e0 h 000fffe0 h coprocessor error trap 8 08 ? 3dc h 000fffdc h inte instruction 9 09 ? 3d8 h 000fffd8 h system reserved 10 0a ? 3d4 h 000fffd4 h system reserved 11 0b ? 3d0 h 000fffd0 h step trace trap 12 0c ? 3cc h 000fffcc h nmi request (tool) 13 0d ? 3c8 h 000fffc8 h undefined instruction exception 14 0e ? 3c4 h 000fffc4 h nmi request 15 0f ? 3c0 h 000fffc0 h external interrupt 0 16 10 icr00 3bc h 000fffbc h external interrupt 1 17 11 icr01 3b8 h 000fffb8 h external interrupt 2 18 12 icr02 3b4 h 000fffb4 h external interrupt 3 19 13 icr03 3b0 h 000fffb0 h external interrupt 4 20 14 icr04 3ac h 000fffac h external interrupt 5 21 15 icr05 3a8 h 000fffa8 h external interrupt 6 22 16 icr06 3a4 h 000fffa4 h external interrupt 7 23 17 icr07 3a0 h 000fffa0 h reload timer 0 24 18 icr08 39c h 000fff9c h reload timer 1 25 19 icr09 398 h 000fff98 h base timer 0 (source 0/source 1) 26 1a icr10 394 h 000fff94 h multi-function serial interface 0 (uart transmission completed/reception completed/i 2 c status) 27 1b icr11 390 h 000fff90 h multi-function serial interface 1 (uart transmission completed/reception completed/i 2 c status) 28 1c icr12 38c h 000fff8c h base timer 1 (source 0/source 1) 29 1d icr13 388 h 000fff88 h
mb91470/480 series 53 (continued) interrupt source interrupt number interrupt level offset tbr default address decimal hexa- decimal base timer 2/3 (source 0/source 1) up/down counter 0 30 1e icr14 384 h 000fff84 h dtti0/dtti1 31 1f icr15 380 h 000fff80 h dmac0 (end/error) 32 20 icr16 37c h 000fff7c h dmac1 (end/error) 33 21 icr17 378 h 000fff78 h dmac2/3/4 (end/error) 34 22 icr18 374 h 000fff74 h multi-function serial interface 2 (uart transmission completed/reception completed/i 2 c status) 35 23 icr19 370 h 000fff70 h multi-function serial interface 3 (uart transmission completed/reception completed/i 2 c status) 36 24 icr20 36c h 000fff6c h multi-function serial interface 4 (uart transmission completed/reception completed/i 2 c status) 37 25 icr21 368 h 000fff68 h multi-function serial interface 5 (uart transmission completed/reception completed/i 2 c status) 38 26 icr22 364 h 000fff64 h mac 39 27 icr23 360 h 000fff60 h ppg0/ppg1 40 28 icr24 35c h 000fff5c h ppg2/ppg3/ppg8/ppg9 41 29 icr25 358 h 000fff58 h ppg4/ppg5/ppg10/ppg11 42 2a icr26 354 h 000fff54 h ppg6/ppg7/ppg12/ppg13/ppg14/ppg15 43 2b icr27 350 h 000fff50 h wave form generator 0/3 (underflow) 44 2c icr28 34c h 000fff4c h wave form generator 1/4 (underflow) 45 2d icr29 348 h 000fff48 h wave form generator 2/5 (underflow) 46 2e icr30 344 h 000fff44 h timebase timer overflow 47 2f icr31 340 h 000fff40 h external interrupt 8/9/10/11/12/13/14/15 48 30 icr32 33c h 000fff3c h free-run timer 0/3 (compare clear) 49 31 icr33 338 h 000fff38 h free-run timer 0/3 (zero detection) 50 32 icr34 334 h 000fff34 h free-run timer 1/4 (compare clear) 51 33 icr35 330 h 000fff30 h free-run timer 1/4 (zero detection) 52 34 icr36 32c h 000fff2c h free-run timer 2/5 (compare clear) 53 35 icr37 328 h 000fff28 h free-run timer 2/5 (zero detection) 54 36 icr38 324 h 000fff24 h 8/10-bit a/d converter 2 55 37 icr39 320 h 000fff20 h 8/10-bit a/d converter 0/ 12-bit a/d converter 3 56 38 icr40 31c h 000fff1c h
mb91470/480 series 54 (continued) interrupt source interrupt number interrupt level offset tbr default address decimal hexa- decimal 8/10-bit a/d converter 1/ 12-bit a/d converter 4 57 39 icr41 318 h 000fff18 h icu0/icu1/icu4/icu5 (capture) 58 3a icr42 314 h 000fff14 h icu2/icu3/icu6/icu7 (capture) 59 3b icr43 310 h 000fff10 h ocu0/ocu1/ocu6/ocu7 (match) 60 3c icr44 30c h 000fff0c h ocu2/ocu3/ocu8/ocu9 (match) 61 3d icr45 308 h 000fff08 h ocu4/ocu5/ocu10/ocu11 (match) 62 3e icr46 304 h 000fff04 h interrupt delay source bit 63 3f icr47 300 h 000fff00 h system reserved (used by realos) 64 40 ? 2fc h 000ffefc h system reserved (used by realos) 65 41 ? 2f8 h 000ffef8 h system reserved 66 42 ? 2f4 h 000ffef4 h system reserved 67 43 ? 2f0 h 000ffef0 h system reserved 68 44 ? 2ec h 000ffeec h system reserved 69 45 ? 2e8 h 000ffee8 h system reserved 70 46 ? 2e4 h 000ffee4 h system reserved 71 47 ? 2e0 h 000ffee0 h system reserved 72 48 ? 2dc h 000ffedc h system reserved 73 49 ? 2d8 h 000ffed8 h system reserved 74 4a ? 2d4 h 000ffed4 h system reserved 75 4b ? 2d0 h 000ffed0 h system reserved 76 4c ? 2cc h 000ffecc h system reserved 77 4d ? 2c8 h 000ffec8 h system reserved 78 4e ? 2c4 h 000ffec4 h system reserved 79 4f ? 2c0 h 000ffec0 h used by int instruction 80 to 255 50 to ff ? 2bc h to 000 h 000ffebc h to 000ffc00 h
mb91470/480 series 55 pin status in each cpu state terms used as the status of pins mean as follows. input enabled means that the input function can be used. input fixed to ?0? a state of a pin, in which "0" is transmitted to internal ci rcuitry, with the external input shut off by the input gate adjacent to the pin. output hi-z means to place a pin in a high impedance state by disabling the pin driving transistor from driving. output storage means to output the state existing imm ediately prior to entering this mode. that is, to output according to an internal resource with an output when it is oper ating or to preserve an output when the output is provided, for example, as a port. preserving the previous state means to be able to output or input the state existing immediately prior to entering this mode.
mb91470/480 series 56 ? list of pin status (continued) pin name function during initialization in sleep mode in stop mode initx = ?l?* 1 initx = ?h?* 2 hiz = 0 hiz = 1 p00 to p07 d16 to d23 output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed p10 to p17 d24 to d31 p20 to p27 a00 to a07 p30 to p37 a08 to a15 p50 to p52 cs0x to cs2x p53 asx p54 rdx p55, p56 wr0x, wr1x p60 sysclk p61 rdy nmix nmix input enabled input enabled in put enabled input enabled input enabled p80 to p83 int0 to int3 output hi-z/ input disabled output hi-z/ input enabled input enabled input enabled input enabled (only when external interrupt is enabled) p84 int4/ppg4 p85 int5/ppg5 p86 int6/ppg6 p87 int7/ppg7 p90 int8/ppg8 p91 int9/ppg9 p92 int10/ppg10 p93 int11/ppg11 p94 int12/ppg12 p95 int13/ppg13 p96 int14/ppg14 p97 int15/ppg15 pa0 to pa4 adtg0 to adtg4 output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed pb0 to pb3 an0-0 to an0-3 output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed pb4 to pb7 an1-0 to an1-3 pc0 an2-0/sck4 pc1 an2-1/sin4 pc2 an2-2/sot4 pc3 an2-3/sck5 pc4 an2-4/sin5 pc5 an2-5/sot5 pc6, pc7 an2-6, an2-7
mb91470/480 series 57 (continued) *1 : initx = ?l? : indicates the pin status with initx remaining at the ?l? level. *2 : initx = ?h? : indicates the pin status existing i mmediately after initx transition from ?l? to ?h? level. pin name function during initialization in sleep mode in stop mode initx = ?l?* 1 initx = ?h?* 2 hiz = 0hiz = 1 pd0 to pd3 an2-8 to an2-11 output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed pe0 to pe3 an3-0 to an3-3 pe4 to pe7 an4-0 to an4-3 pf0 clkpout output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed pf1 to pf6 gpio pg0, pg3 sck0, sck1 output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed pg1, pg4 sin0, sin1 pg2, pg5 sot0, sot1 ph0, ph3 sck2, sck3 ph1, ph4 sin2, sin3 ph2, ph5 sot2, sot3 pj0, pj2, pj4, pj6 tin0 to tin3 output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed pj1, pj3, pj5, pj7 tout0 to tout3 pl0 ain0 output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed pl1 bin0 pl2 zin0 pm0 to pm3 ppg0 to ppg3 output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed pp0 to pp3 ic0 to ic3 output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed pp4 cki0 pp5 dtti0 pq0 to pq5 rto0 to rto5 pr0 to pr3 ic4 to ic7 output hi-z/ input disabled output hi-z/ input disabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input ?0? fixed pr4 cki1 pr5 dtti1 ps0 to ps5 rto6 to rto11
mb91470/480 series 58 ? list of pin status (external bus mode) *1 : initx = ?l? : indicates the pin status with initx remaining at the ?l? level. *2 : initx = ?h? : indicates the pin status existing immediately after in itx transition from ?l? to ?h? level. pin name function during initialization in sleep mode in stop mode initx = ?l?* 1 initx = ?h?* 2 hiz = 0hiz = 1 p00 to p07 d16 to d23 output hi-z output hi-z retention of the immediately prior state retention of the immediately prior state output hi-z p10 to p17 d24 to d31 p20 to p27 a00 to a07 p30 to p37 a08 to a15 p50 to p52 cs0x to cs2x p53 asx p54 rdx p55, p56 wr0x, wr1x p60 sysclk p61 rdy input disabled input disabled input ?0? fixed
mb91470/480 series 59 electrical characteristics 1. absolute maximum ratings *1 : the parameter is based on vss = avss10 = avss12 = 0 v. *2 : be careful not to exceed vcc + 0.3 v, for example, when the power is turned on. be careful to set avcc10, avcc12 equal vcc, for example, when the power is turned on. *3 : the maximum output current is the peak value for a single pin. *4 : the average output is the average current for a single pin over a period of 100 ms. *5 : the total average output cu rrent is the average current for all pins over a period of 100 ms. *6 : avcc10 is the analog supply voltage for the 8/10-bit a/d converter, and avcc12 is the analog supply voltage for the 12-bit a/d converter. *7 : avrhn=avrh0/avrh1/avrh2 are the analog referenc e voltage for the 8/10-bit a/d converter, and avrh3/ avrh4 are the analog reference voltage for the 12-bit a/d converter. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage* 1 vcc vss ? 0.5 vss + 6.0 v analog power supply voltage* 1, * 2, * 6 avcc10 avcc12 vss ? 0.5 vss + 6.0 v analog reference voltage* 7 avrhn vss ? 0.5 vss + 6.0 v input voltage* 1 v i vss ? 0.3 vcc + 0.3 v analog pin input voltage* 1 v ia vss ? 0.3 avcc + 0.3 v output voltage* 1 v o vss ? 0.3 vcc + 0.3 v ? l ? level maximum output current* 3 i ol ? 10 ma ?l? level average output current* 4 i olav ? 4 ma except port q0 to q5 and s0 to s5 12 ma port q0 to q5 and s0 to s5 ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current* 5 i olav ? 50 ma ?h? level maximum output current* 3 i oh ?? 10 ma ?h? level average output current * 4 i ohav ? ? 4 ma except port q0 to q5 and s0 to s5 ? 12 ma port q0 to q5 and s0 to s5 ?h? level total maximum output current i oh ?? 100 ma ?h? level total average output current* 5 i ohav ?? 50 ma power consumption p d ? 800 mw storage temperature t stg ? 55 + 125 c
mb91470/480 series 60 2. recommended operating conditions (vss = avss10 = avss12 = 0.0 v) * : the remaining rating values assume four-layer pcb. note : during power-on, it takes approximately 600 s for the internal power supply to stabilize after the v cc power supply has stabilized. continue to asse rt the initx pin during this period. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage vcc 4.0 5.5 v analog power supply voltage avcc10 vss + 4.0 vss + 5.5 v for all 8/10-bit a/d converter (common use) avcc12 vss + 4.0 vss + 5.5 v for all 12-bit a/d converter (common use) analog reference voltage avrh0 avss10 avcc10 v for 8/10-bit a/d converter 0 avrh1 avss10 avcc10 v for 8/10-bit a/d converter 1 avrh2 avss10 avcc10 v for 8/10-bit a/d converter 2 avrh3 avss12 avcc12 v for 12-bit a/d converter 3 avrh4 avss12 avcc12 v for 12-bit a/d converter 4 (-) analog input signal voltage range aninn avss12 avcc12/2 v for all 12-bit a/d converters (common use) (under differential mode) ( + ) analog input signal voltage range aninp avss12 avcc12 v aninn-aninp voltage difference aninn ? aninp ? avcc12/4 v operating temperature t a ? 40 + 70 c when mounted on single-layer pcb* + 85 when mounted on four-layer pcb*
mb91470/480 series 61 3. dc characteristics (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v) (continued) parameter symbol pin conditions value unit remarks min typ max ?h? level input voltage v ih cmos input pin ? vcc 0.7 ? vcc v v ihs cmos hysteresis input pin ? vcc 0.8 ? vcc v ?l? level input voltage v il cmos input pin ? vss ? vcc 0.3 v v ils cmos hysteresis input pin ? vss ? vcc 0.2 v ?h? level output voltage v oh1 except port q0 to q5 and port s0 to s5 vcc = 5.0 v, i oh = 4 ma vcc ? 0.5 ?? v v oh2 port q0 to q5 and port s0 to s5 vcc = 5.0 v, i oh = 12 ma vcc ? 0.5 ?? v ?l? level output voltage v ol1 except port q0 to q5 and port s0 to s5 vcc = 5.0 v, i ol = 4 ma ?? vss + 0.4 v v ol2 port q0 to q5 and port s0 to s5 vcc = 5.0 v, i ol = 12 ma ?? vss + 0.4 v input leak current i li ? vcc = 5.0 v, vss < v i < vcc ? 5 ?? a pull-up resistance r pull initx, pull-up pin ?? 50 ? k ? power supply current i cc vcc flash memory vcc = 5.0 v, f c = 20 mhz, pll 4, clkb = 80 mhz clkp = 40 mhz clkt = 40 mhz ? 100 ? ma when the multiply and accumulate unit is not used. ? 140 ? ma when the multiply and accumulate unit is used.
mb91470/480 series 62 (continued) (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v) parameter symbol pin conditions value unit remarks min typ max power supply current i cc vcc mask rom vcc = 5.0 v, f c = 20 mhz, pll 4, clkb = 80 mhz clkp = 40 mhz clkt = 40 mhz ? 65 ? ma when the multiply and accumulate unit is not used. ? 105 ? ma when the multiply and accumulate unit is used. i ccs vcc vcc = 5.0 v, f c = 20 mhz, pll 4, clkb = 80 mhz clkp = 40 mhz clkt = 40 mhz ? 50 ? ma in sleep mode (when multiplication and addition calculator circuit is not used.) ? 80 ? ma in sleep mode (when multiplication and addition calculator circuit is used.) i cch vcc vcc = 5.0 v, t a = + 25 c ? 350 ? a in stop mode vcc = 5.0 v, t a = + 85 c ? 1500 ? a in stop mode input capacitance c in other than vcc, vss, avss12, avss10, avcc12, avcc10, avrh0, avrh1, avrh2, avrh3, avrh4 ?? 515pf
mb91470/480 series 63 4. flash memory write/erase characteristics parameter conditions value unit remarks min typ max sector erase time (8 kbytes sectors) vcc = 5.0 v, t a = + 25 c ? 0.5 2.0 s not including time for internal writing before deletion. word write time vcc = 5.0 v, t a = + 25 c ? 6 100 s not including system-level overhead time. chip write time vcc = 5.0 v, t a = + 25 c ? 1.8 29.5 s not including system-level overhead time. erase/write cycle ? 10000 ?? cycle flash memory data hold time ? 10 ?? year
mb91470/480 series 64 5. ac characteristics (1) clock timing (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v) *1 : the values assume a gear cycle of 1/16. *2 : when the pll is used, the pll multiplication rate varies depending on the fr equency of the clock input to the x0 and x1 pins. set the pll multiplication rate so that the pll output clock frequency is in the range between 40 mhz and 80 mhz. ? conditions for measuring the clock timing ratings parameter sym- bol pin name condition value unit remarks min typ max clock frequency f c x0 x1 ? 10* 2 ? 20 mhz when using the pll within the self-oscillating range, set the multiplier so that the internal clock does not exceed the internal oper- ating clock fre- quency. clock cycle time t c x0 x1 100 ? 50* 2 ns internal operating clock frequency f cp ? when 20 mhz is input as the x0 clock frequency and the oscillator circuit pll system is set to 4 multiplication 5* 1 ? 80 mhz cpu f cpp 5* 1 ? 40 mhz peripheral f cpt 5* 1 ? 40 mhz external bus internal operating clock cycle time t cp ? 12.5 ? 200 ns cpu t cpp 25 ? 200 ns peripheral t cpt 25 ? 200 ns external bus pll multiplication rate 1 2 3 4 5 6 7 8 pll output clock frequency when x0 = 10 mhz (setting not allowed) 40 mhz 50 mhz 60 mhz 70 mhz 80 mhz pll output clock frequency when x0 = 20 mhz (setting not allowed) 40 mhz 60 mhz 80 mhz (setting not allowed) 0.8 vcc 0.2 vcc t cf t cr t c p wh p wl c = 50 pf output pin
mb91470/480 series 65 ? operation assurance range ? internal clock setting range 0 5.5 4.0 f cp s (mhz) 8 0 0. 3 1 vcc (v) internal clock power supply voltage but the upper limit of f cp /f cpp is 40 mhz. 80 (mhz) 40 5 16 :16 2 : 2 1 : 2 cpu (clkb) : peripheral (clkp) external bus (clkt) : internal clock notes : ? when the pll is used, the external clock inpu t should be in the range of 10 mhz to 20 mhz. ? treat the pll oscillation stabilization time as > 600 s ? set the internal clock gear setting to within th e values shown in the clock timing ratings table. oscillation input clock f c = 20 mhz cpu : divided ratio for peripherals/external bus. (pll multiplied by 4)
mb91470/480 series 66 (2) clock output timing (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) *1 : t cyc is the frequency of one clock cycle including the gear cycle. *2 : the following ratings are for the gear ratio set to 2. for the ratings when the gear ratio is set to 1/4 and 1/8, can be calculated by substituting 1/4 or 1/8 for n respectively in the following equation. (1/2 1/n) t cyc -5 note : for t cpt (internal clock cycle time) , refer to ?(1) clock timing?. (3) pll oscillation stabilization time (lock up time) (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) * : the length of time to wait for the pll oscillations to stabilize. parameter symbol pin name condi- tion value unit remarks min max cycle time t cyc sysclk ? t cpt ? ns *1 sysclk sycsclk t chcl t cyc /2 ? 5t cyc /2 + 5ns*2 sysclk sycsclk t clch t cyc /2 ? 5t cyc /2 + 5ns parameter symbol pin name condition value unit min max pll oscillation stabilization wait time (lock up time) t lock * ?? 600 ? s v oh t chcl t cyc t clch v oh v ol s y s clk
mb91470/480 series 67 (4) reset input ratings (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) notes : ? it takes approximately 600 s for the internal power to stabilize after the power supply has stabilized. continue to input ?l? to the initx pin during this period. ? for t cpt (internal clock cycle time) , refer to ?(1) clock timing?. parameter symbol pin name condition value unit min max initx input time (at power-on and stop mode) t intl initx ? oscillation time of oscillator tc 10 ? ns initx input time (other than the above) tc 10 ? ns initx 0.2 vcc t intl
mb91470/480 series 68 (5) normal bus access read/write operation (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condi- tion value unit remarks min max asx setup t aslch sysclk asx ? 3 ? ns asx hold t chash 31/2 t cyc + 10 ns cs0x to cs2x setup t cslch sysclk cs0x to cs2x ? 3 ? ns cs0x to cs2x hold t chcsh 31/2 t cyc + 10 ns address setup t asch sysclk a15 to a00 ? 3 ? ns t asrl rdx a15 to a00 3 ? ns t aswl wr0x, wr1x a15 to a00 3 ? ns address hold t chax sysclk a15 to a00 ? 31/2 t cyc + 10 ns t rhax rdx a15 to a00 3 ? ns t whax wr0x, wr1x a15 to a00 3 ? ns valid address valid data input time t avdv a15 to a00 d31 to d16 ?? 3/2 t cyc ? 7ns *1 *2 rdx delay time t chrl sysclk rdx ?? 10 ns t chrh ?? 10 ns rdx valid data input time t rldv rdx d31 to d16 ? ? t cyc ? 5ns*1 data setup rdx time t dsrh 18 ? ns rdx data hold time t rhdx 0 ? ns rdx minimum pulse width t rlrh rdx ? t cyc ? 5 ? ns wr0x, wr1x delay time t chwl sysclk rdx ? ? 10 ns t chwh ? 10 ns data setup wr0x, wr1x time t dswh wr0x, wr1x d31 to d16 ? t cyc ? ns wr0x, wr1x data hold time t whdx 3 ? ns wr0x, wr1x minimum pulse width t wlwh wr0x, wr1x ? t cyc ? 5 ? ns
mb91470/480 series 69 (continued) *1 : when the bus timing is delayed by an automati c wait instruction or rdy input, add the time (t cyc the number of delay cycles added) to this rating. *2 : the following ratings are for the gear ratio set to 2. for the ratings when the gear ratio is set to between 1/3 and 1/16, substitute the value between 1/ 3 and 1/16 for n in the following equation. formula : 3/ (2n) t cyc ? 15 note : load capacitance c = 50 pf v oh s y s clk v oh a s x c s 0x to c s 2x a15 to a00 rdx d 3 1 to d16 (re a d) wr0x, wr1x d 3 1 to d16 (write) v oh v oh v oh v oh v oh v oh t a s lch t cha s h t c s lch t chc s h t a ss ch t chax t chrl t cyc t rlrh t chrh t rhax t rldv t d s rh t a s rl t avdv t chwl t wlwh t chwh t a s wl t whax t whdx t d s wh v oh v oh v ol v ol v ol v ol v ol v ol v ol v oh v ol t rhox v oh v ol t aslch t asch t rhdx
mb91470/480 series 70 (6) multiplex bus access read/write operation (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) notes : ? this rating is not guaranteed when the csx rdx/wrx setup delay setting by awr : bit1 is ?0?. ? normal bus interface ratings are applicable except this rating. ? for t cyc (cycle time), refer to ?(2) clock output timing?. parameter symbol pin name condition value unit min max a15 to a00 address setup time sysclk t asch sysclk, d31 to d16 ? 3 ? ns sysclk a15 to a00 address hold time t chax 31/2 t cyc + 10 ns a15 to a00 address setup time asx t asash asx, d31 to d16 12 ? ns asx a15 to a00 address hold time t ashax t cyc ? 5t cyc + 5ns t cyc s y s clk a s x d 3 1 to d16 (a15 to a00) t a s a s h t chah t a s ch t a s hax v oh v oh v ol v oh v oh v ol
mb91470/480 series 71 (7) ready input timing (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit min max rdy setup time sysclk t rdys sysclk, rdy ? 18 ? ns sysclk rdy hold time t rdyh 0 ? ns sysclk v oh v oh v ol v ol v ol v oh v ol v oh v oh v ol v oh v ol t rdyh t rdyh rdy rdy t cyc t rdys t rdys (when wait is used) (when wait is not used)
mb91470/480 series 72 (8) uart timing (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) notes : ? the above ratings are the ac char acteristics for clk synchronous mode. ? t cycp indicates the peripheral clock cycle time. parameter symbol pin conditions value unit min max serial clock cycle time t scyc sck0 to sck5 internal shift clock mode 8 t cycp ? ns sck sot delay time t slov sck0 to sck5 sot0 to sot5 ? 50 + 50 ns valid sin sck t ivsh sck0 to sck5 sin0 to sin5 50 ? ns sck valid sin hold time t shix sck0 to sck5 sin0 to sin5 0 ? ns serial clock ?h? pulse width t shsl sck0 to sck5 external shift clock mode 4 t cycp ? ns serial clock ?l? pulse width t slsh sck0 to sck5 4 t cycp ? ns sck sot delay time t slov sck0 to sck5 sot0 to sot5 ? 50 ns valid sin sck t ivsh sck0 to sck5 sin0 to sin5 50 ? ns sck valid sin hold time t shix sck0 to sck5 sin0 to sin5 50 ? ns
mb91470/480 series 73 ? internal shift clock mode ? external shift clock mode sck0 to sck5 t scyc t slov t ivsh t shix v ol v ol v oh v oh v ol v oh v ol v oh v ol sot0 to sot5 sin0 to sin5 t slsh t slov t ivsh t shix t shsl v oh v ol v oh v ol v oh v ol v oh v ol v ol v ol sck0 to sck5 sot0 to sot5 sin0 to sin5
mb91470/480 series 74 (9) free-run timer clock, up/down counter, base timer, and external interrupt input timing (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) note : t cycp indicates the peripheral clock cycle time. parameter symbol pin name condition value unit min max free-run timer input clock pulse width t tiwh t tiwl cki0, cki1 ? 4 t cycp ? ns up-down counter input pulse width ain0 bin0 zin0 4 t cycp ? ns base timer input pulse width tin0 to tin3 4 t cycp ? ns external interrupt input pulse width int0 to int15 4 t cycp ? ns 1.0 ? s t tiwl t tiwh v oh v oh v ol v ol cki0, cki1 ain0, bin0, zin0 tin0 to tin 3 int0 to int15
mb91470/480 series 75 (10) trigger input timing (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) note : t cycp indicates the peripheral clock cycle time. parameter symbol pin name condition value unit min max input capture trigger input t icwh t icwl ic0 to ic7 ? 5 t cycp ? ns base timer trigger input t tginwh t tginwl tin0 to tin3 4 t cycp ? ns a/d activation trigger input t adtgwh t adtgwl adtg0 to adtg4 5 t cycp ? ns ic0 to ic7 tin0 to tin 3 adtg0 to adtg4 t icwh t tginwh t adtgwh t icwl t tginwl t adtgwl v oh v oh v ol v ol
mb91470/480 series 76 (11) i 2 c timing a. master mode (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) *1 : t cycp indicates the peripheral clock cycle time. *2 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 250 ns must then be met. if a device does not extend the ?l? period of the scl signal, it is necessary to output the next piece of data to the sda line 1250 ns (sda and scl rising max time + t sudata ) before the scl line is released. *3 : for use at over 100 khz, set t he resource clock to at least 6 mhz. *4 : r and c are the pull-up resistance and l oad capacitance of the scl and sda lines. parameter symbol condition standard mode fast mode * 3 unit remarks minmaxminmax scl clock frequency f scl r=1 k ? , c=50 pf* 4 0 100 0 400 khz ?l? width of the scl clock t low 4.7 ? 1.3 ? ms ?h? width of the scl clock t high 4.0 ? 0.6 ? ms bus free time between stop and start conditions t bus 4.7 ? 1.3 ? ms scl sda output delay time t dldat ? 5 t cycp * 1 ? 5 t cycp * 1 ns setup time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? ms hold time for a repeated start condition sda scl t hdsta 4.0 ? 0.6 ? ms the first clock pulse is generated after this. setup time for stop condition scl sda t susto 4.0 ? 0.6 ? ms sda data input hold time (vs. scl ) t hddat 2 t cycp * 1 ? 2 t cycp * 1 ? ms sda data input setup time (vs. scl ) t sudat 250 ? 100 * 2 ? ns
mb91470/480 series 77 b. slave mode (vcc = 4.0 v to 5.5 v, vss = avss10 = avss12 = 0.0 v, t a = ? 40 c to + 85 c) *1 : t cycp indicates the peripheral clock cycle time. *2 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 250 ns must then be met. if a device does not extend the ?l? period of the scl signal, it is necessary to output the next piece of data to the sda line 1250 ns (sda and scl rising max time + t sudata ) before the scl line is released. *3 : for use at over 100 khz, set t he resource clock to at least 6 mhz. *4 : r and c are pull-up resistance and lo ad capacitance of the scl and sda lines. parameter symbol condition standard mode fast mode * 3 unit remarks minmaxminmax scl clock frequency f scl r=1 k ? , c=50 pf* 4 01000400khz ?l? width of the scl clock t low 4.7 ? 1.3 ? s ?h? width of the scl clock t high 4.0 ? 0.6 ? s bus free time between stop and start conditions t bus 4.7 ? 1.3 ? s scl sda output delay time t dldat ? 5 t cycp * 1 ? 5 t cycp * 1 ns setup time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? s hold time for a repeated start condition sda scl t hdsta 4.0 ? 0.6 ? s the first clock pulse is generated after this. setup time for stop condition scl sda t susto 4.0 ? 0.6 ? s sda data input hold time (vs scl ) t hddat 2 t cycp * 1 ? 2 t cycp * 1 ? s sda data input setup time (vs. scl ) t sudat 250 ? 100 * 2 ? ns
mb91470/480 series 78 6. electrical characteristics for the a/d converter (1) 8/10-bit a/d converter (vcc = 4.0 v to 5.5 v, avrhn = 4.0 v to 5.5 v, vss = avss10 = 0 v, t a = ? 40 c to + 85 c) *1 : when vcc = avcc10 = 5.0 v and machine clock = 33 mhz *2 : the current when the cpu is in stop mode and the a/d converter is not operating (at vcc = avcc10 = avrhn = 5.0 v) . notes : ? the above figures do not guarant ee the accuracy between each unit. ? output impedance of the external circuit 2 k ? . ? avrhn = avrh0, avrh1, and avrh2 parameter sym- bol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? 4 ? + 4lsb when avrhn = 5.0 v linearity error ?? ? 3.5 ? + 3.5 lsb differential linearity error ?? ? 3 ? + 3lsb zero transition voltage v ot an0-0 to an0-3 an1-0 to an1-3 an2-0 to an2-11 avss10 ? 3.5 avss10 + 0.5 avss10 + 4.5 lsb full-scale transition voltage v fst an0-0 to an0-3 an1-0 to an1-3 an2-0 to an2-11 avrhn ? 5.5 avrhn ? 1.5 avrhn + 2.5 lsb conversion time* 1 ?? 1.2 ?? s analog port input current i ain an0-0 to an0-3 an1-0 to an1-3 an2-0 to an2-11 ?? 10 a analog input voltage v ain an0-0 to an0-3 an1-0 to an1-3 an2-0 to an2-11 avss10 ? avrhn v reference voltage ? avrhn avss10 ? avcc10 v power supply current (analog + digital) i a avcc10 ? 2 ? ma for each 1 unit i ah * 2 avcc10 ?? 5 a reference voltage supply current (between avrh and avss) i r avrhn ? 1 ? ma for each 1 unit, at avrhn = 5.0 v avss10 = 0 v i rh * 2 avrhn ?? 5 a for each 1 unit, at stop mode analog input capacitance ?? ? ? 12.5 pf interchannel disparity ? an0-0 to an0-3 an1-0 to an1-3 an2-0 to an2-11 ?? 4lsb
mb91470/480 series 79 (2) 12-bit a/d converter (vcc = 4.0 v to 5.5 v, avrhn = 4.0 v to 5.5 v, vss = avss12 = 0 v, t a = ? 40 c to + 85 c) * : the current when the cpu is in stop mode and the a/d converter is not operating (at vcc = avcc10 = avrhn = 5.0 v) . notes : ? the above figures do not guarant ee the accuracy between each unit. ? output impedance of the external circuit 2 k ? ? avrhn = avrh3, avrh4 parameter symbol pin name value unit remarks min typ max resolution ?? ?? 12 bit linearity error ?? ? 3.6 ? + 3.6 lsb when avrhn = 5.0 v differential linearity error ?? ? 3 ? + 3lsb zero transition voltage v ot an3-0 to an3-3 an4-0 to an4-3 typ ? 20 [mv] avss 12 + 0.5 [lsb] typ + 20 [mv] ? full-scale transition voltage v fst an3-0 to an3-3 an4-0 to an4-3 typ ? 20 [mv] avrhn ? 1.5 [lsb] typ + 20 [mv] ? conversion time ?? 2.0 ?? s when machine clock = 33 mhz 2.2 ?? s when machine clock = 40 mhz analog port input current i ain an3-0 to an3-3 an4-0 to an4-3 ?? 10 a analog input voltage v ain an3-0 to an3-3 an4-0 to an4-3 avss12 ? avrhn v reference voltage ? avrhn avss12 ? avcc12 v analog supply current (analog + digital) i a avcc12 ? 2 ? ma for each unit i ah *avcc12 ?? 5 a reference voltage supply current (between avrh and avss) i r avrhn ? 1 ? ma for each unit, at avrhn = 5.0 v, avss12 = 0 v i rh * avrhn ?? 5 a for each unit, at stop mode analog input capacitance ?? ?? 18 pf interchannel disparity ? an3-0 to an3-3 an4-0 to an4-3 ?? 4lsb
mb91470/480 series 80 ? external impedance and sampling time of analog inputs the a/d converter is fitted with a sample and hold circui t. if the external impedance is so high that there is not sufficient time for sampling, the internal sample and ho ld capacitor will not fully charge to the analog voltage, and the precision of the a/d conversion will be adversely affected. theref ore, in order to satisfy the a/d conversion precision specifications, either adjust the register values and operating frequency or reduce the external impedance so that the sampling time is greater than the minimum value as given by the relationship between external impedance and minimum sampling time . if you are still unable to hold enough sampling time, connect a capacitor of about 0.1 f to the analog input pin. to satisfy the a/d conversion precision standard, cons ider the relationship between the external impedance and minimum sampling time and either adjust the resi stor value and operating frequency or decrease the external impedance so that the sampling ti me is longer than the minimum value. ? about errors the relative error increases as the value of |avrh ? avss| decreases. r c comp a r a tor 8/10-bit a/d converter 12-bit a/d converter r 4.6 k ? 1.0 k ? c 12.5 pf 18.0 pf ? analog input circuit schematic during sampling : on analog input note : the values are reference values. 8/10-bit a/d converter 12-bit a/d converter 100 90 80 70 60 50 40 30 20 10 0 8/10-bit a/d converter 12-bit a/d converter 20 18 16 14 12 10 8 6 4 2 0 024 14 12 10 8 6 0 0.4 0.8 2.8 2.4 2.0 1.6 1.2 3.2 ? the relationship between the external impedance and minimum sampling time (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s]
mb91470/480 series 81 ? definition of 8/10-bit a/d converter terms resolution : analog variation that is recognized by the a/d converter. linearity error : deviation between t he line connecting zero transition point (0000000000 0000000001) and full-scale transition point (1111111110 1111111111) and actual conversion characteristics. differential linear error : deviation from the ideal valu e of input voltage necessary to change the output code by ilsb. total error : this error is the difference betw een actual and ideal values, including the zero transition error/full-scale transition error/linearity error. (continued) fff h ffe h ffd h 004 h 003 h 002 h 001 h av ss avrh {1 lsb (n ? 1) + v ot } av ss avr h n ? 2 h n ? 1 h n h n + 1 h actual conversion characteristic v fst (measurement value) v nt v ot v (n+1)t v nt actual conversion characteristic actual conversion characteristic actual conversion characteristic (measurement value) (measurement value) (measurement value) (measurement value) ideal characteristic ideal characteristic linearity error differential linear error digital output digital output analog input analog input n : a/d converter digital output value v ot : voltage at which digital output changes from 000 h to 001 h . v fst : voltage at which digital output changes from 3fe h to 3ff h . v nt : voltage at which digital output changes from (n ? 1) to n. linear error in digital output n = v nt ? {1 lsb (n ? 1) + v ot } [lsb] 1 lsb differential linear error in digital output n = v ( n + 1 ) t ? v nt ? 1 [lsb] 1 lsb 1 lsb = v fst ? v ot 1022
mb91470/480 series 82 (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh 1.5 lsb' 0.5 lsb' {1 lsb' (n ? 1) + 0.5 lsb'} v nt actual conversion characteristic actual conversion characteristic (measurement value) ideal characteristic total error digital output analog input n : a/d converter digital output value v nt : voltage at which digi tal output changes from (n + 1) to n. v ot ? (ideal value) = av ss + 0.5 lsb? [v] v fst ? (ideal value) = avrh ? 1.5 lsb? [v] 1 lsb? (ideal value) = avrh ? av ss [v] 1024 total error of digital output n = v nt ? {1 lsb? (n ? 1) + 0.5 lsb?} 1 lsb?
mb91470/480 series 83 ? definition of 12-bit a/d converter terms resolution : analog variation that is recognized by the a/d converter. linearity error : deviation between t he line connecting zero transition point (000000000000 000000000001) and full-scale transition point (111111111110 111111111111) and actual conversion characteristics. differential linear error : deviation from the ideal value of input voltage necessary to the output code by ilsb. fff h ffe h ffd h 004 h 003 h 002 h 001 h av ss avrh {1 lsb (n ? 1) + v ot } av ss avr h n ? 2 h n ? 1 h n h n + 1 h actual conversion characteristic v fst (measurement value) v nt v ot v (n+1)t v nt actual conversion characteristic actual conversion characteristic actual conversion characteristic (measurement value) (measurement value) (measurement value) (measurement value) ideal characteristic ideal characteristic linearity error differential linear error digital output digital output analog input analog input n : a/d converter digital output value v ot : voltage at which digital output changes from 000 h to 001 h . v fst : voltage at which digital output changes from ffe h to fff h . v nt : voltage at which digital output changes from (n ? 1) to n. linear error in digital output n = v nt ? {1 lsb? (n ? 1) + v ot } [lsb] 1 lsb? differential linear error in digital output n = v ( n + 1 ) t ? v nt ? 1 [lsb] 1 lsb? 1 lsb = v fst ? v ot 4094
mb91470/480 series 84 ordering information part no. package mb91f475pmc1-ge1 fpt-144p-m12 MB91F475BGL-GE1 bga-144p-m06 mb91f478pmc1-ge1 fpt-144p-m12 mb91f478bgl-ge1 bga-144p-m06 mb91f479pmc1-ge1 fpt-144p-m12 mb91f479bgl-ge1 bga-144p-m06 mb91f487pmc-ge1 fpt-100p-m20 mb91482pmc-ge1 fpt-100p-m20
mb91470/480 series 85 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 100-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 14.0 mm 14.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm m a x weight 0.65 g code (reference) p-lfqfp100-14 14-0.50 100-pin pl as tic lqfp (fpt-100p-m20) (fpt-100p-m20) c 2005 fujit s u limited f1000 3 1 s -c-2-1 14.00 0.10(.551 .004) s q 16.00 0.20(.6 3 0 .00 8 ) s q 1 25 26 51 76 50 75 100 0.50(.020) 0.20 0.05 (.00 8 .002) m 0.0 8 (.00 3 ) 0.145 0.055 (.0057 .0022) 0.0 8 (.00 3 ) "a" index .059 ? .004 +.00 8 ? 0.10 +0.20 1.50 (mo u nting height) 0 ? ~ 8 ? (0.50(.020)) (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.10 (.004 .004) det a il s of "a" p a rt ( s t a nd off) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb91470/480 series 86 please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 144-pin pl as tic lqfp le a d pitch 0.40 mm p a ck a ge width p a ck a ge length 16.0 16.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0. 88 g code (reference) p-lfqfp144-16 16-0.40 144-pin pl as tic lqfp (fpt-144p-m12) (fpt-144p-m12) c 200 3 fujit s u limited f144024 s -c- 3 - 3 .059 ? .004 +.00 8 ? 0.10 +0.20 1.50 det a il s of "a" p a rt 0~ 8 ? (mo u nting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 ( s t a nd off) 0.0 8 (.00 3 ) 0.145 ? 0.0 3 +.002 ? .001 .006 +0.05 "a" .007.001 0.1 8 0.0 3 5 m 0.07(.00 3 ) 3 6 3 7 1 lead no. 0.40(.016) index 144 109 10 8 1 8 .000.20(.709.00 8 ) s q s q 16.00 7 3 72 * .6 3 0 ? .004 +.016 ? 0.10 +0.40 dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s incl u de re s in protr us ion. re s in protr us ion i s +0.25(.010)m a x(e a ch s ide). note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb91470/480 series 87 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 144- ba ll pl as tic pfbga b a ll pitch 0. 8 0 mm p a ck a ge width p a ck a ge length 12.00 12.00 mm le a d s h a pe s oldering ba ll s e a ling method pl as tic mold b a ll s ize ? 0.45 mm mo u nting height 1.45 mm m a x. weight 0. 3 2 g 144- ba ll pl as tic pfbga (bga-144p-m06) (bga-144p-m06) c 200 3 fujit s u limited b144006 s -c-1-1 12.00 0.10 (.472 .004) a b c d e f g h j k l m 1 2 3 4 5 6 7 8 m s ab b ref 0. 8 0(.0 3 1) 9 10 n a 0. 8 0(.0 3 1) ref 144- ? 0.45 0.10 (144- ? .01 8 .004) ? 0.0 8 (.00 3 ) 0.20(.00 8 ) s a (index area) s s 0.10(.004) ( s t a nd off) (.014 .004) 0. 3 5 0.10 ( s e a ted height) 1.25 0.20 (.049 .00 8 ) 0.20(.00 8 ) s b 12.00 0.10(.472 .004) 1 3 12 11 index dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s .
mb91470/480 series f0612 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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